{"id":856679,"url":"http://patchwork.ozlabs.org/api/patches/856679/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20180108024558.17983-29-f4bug@amsat.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20180108024558.17983-29-f4bug@amsat.org>","list_archive_url":null,"date":"2018-01-08T02:45:57","name":"[28/29] piix: merge common code from isa/piix4.c with southbridge piix3","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b75a5078d82e8f64d738228a037567ef864a8e88","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/?format=json","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20180108024558.17983-29-f4bug@amsat.org/mbox/","series":[{"id":21847,"url":"http://patchwork.ozlabs.org/api/series/21847/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=21847","date":"2018-01-08T02:45:30","name":"remove i386/pc dependency: generic SuperIO, PIIX cleanup","version":1,"mbox":"http://patchwork.ozlabs.org/series/21847/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/856679/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/856679/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"LFBYVvJL\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3zFKk75MMBz9s7n\n\tfor ;\n\tMon, 8 Jan 2018 13:59:27 +1100 (AEDT)","from localhost ([::1]:59438 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1eYNek-0000yZ-QH\n\tfor incoming@patchwork.ozlabs.org; Sun, 07 Jan 2018 21:59:22 -0500","from eggs.gnu.org ([2001:4830:134:3::10]:51858)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from )\n\tid 1eYNTZ-0007q0-2i\n\tfor qemu-devel@nongnu.org; Sun, 07 Jan 2018 21:47:52 -0500","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from )\n\tid 1eYNTX-0003Pc-1h\n\tfor qemu-devel@nongnu.org; Sun, 07 Jan 2018 21:47:49 -0500","from mail-qk0-x241.google.com ([2607:f8b0:400d:c09::241]:44110)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1eYNTW-0003PL-SA\n\tfor qemu-devel@nongnu.org; Sun, 07 Jan 2018 21:47:46 -0500","by mail-qk0-x241.google.com with SMTP id v188so12537486qkh.11\n\tfor ; Sun, 07 Jan 2018 18:47:46 -0800 (PST)","from x1.local ([138.117.48.219]) by smtp.gmail.com with ESMTPSA id\n\td10sm7156245qkg.16.2018.01.07.18.47.42\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tSun, 07 Jan 2018 18:47:45 -0800 (PST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=RuRleaNPTZ4g3RGtHoM/VVf6IfBqlBZIoudl06L+1k4=;\n\tb=LFBYVvJLXZckULc03pLNZDCkkFOd7s/sLkp+mULo+QGSdwrFHlqDA7tx2SiDGziN9b\n\t6HQiFVNy8F6MuZMArzTjIYzKyDkXUVe77ONU40F+d5f5Uysa5f43sgLWuj43AbwqSt2K\n\t6iLbLbYUDXYDivGEtI+Hy01iCLFs7Cp90soVTLA+jT+KPKQ4ZjmxBKnKbfZ0STIWbCCD\n\tHcPhS9AKXv5AkCcss3MAZVEaISbgMNTZp3yee+o6dJzzWav6zStqeF4RAahgD+Y0J1Vg\n\tsJBPOL7hyof7I3aSpOZhR/7nsqmZ1fhMURrhVgHmTyw6kpwn5PXy9PaqezZitQ0a1GQE\n\tWJmw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:in-reply-to:references:mime-version:content-transfer-encoding;\n\tbh=RuRleaNPTZ4g3RGtHoM/VVf6IfBqlBZIoudl06L+1k4=;\n\tb=ImN6HpTVBYJhyr9VejORqmAJSEICcN0Vy8dQqX9TQhlu4aV5wZRRynSZNyL9AExQ2V\n\t0DDDB8FBAV4IxD/eW1vp7fjZQZ7UEJw0Vdv7HvSQ6RUPfi8+6lSjvvWfXfjSGAQhDLA4\n\t1p20ZtAqEjGA8Q8c8scyJyTAFSOImfkVDpkZXxzAhSrwqJTCmfTbmTbm1x0iBuTKa+5R\n\tzazDI+/5m8TGI7LitXxgcYP2yKWzcLvPRkx9gTTJMH3RKfttbvq6wF3UrzJLayr6+ufL\n\tIhXleVBuTj+jHURlUFRTkvNn8s4X1TTO4u2dWlV5pYrdyJGpJtp8uIuD4b/ZfCuM6JE0\n\t09zg==","X-Gm-Message-State":"AKGB3mKt+1HGsfhjscA8BdyILEzMYwn0JPuNJ2tA1CDBzyswQmLW+n2v\n\tYk2Z45p0MP5jnB8P7jC6jQg=","X-Google-Smtp-Source":"ACJfBovChyb07P7jv41egKmJV0UJ2xRWjgkPD1C16DUZHe6oLnNMhy38CgS3cm4lXZhFXVWcPIgPZA==","X-Received":"by 10.55.150.198 with SMTP id\n\ty189mr14969021qkd.300.1515379666202; \n\tSun, 07 Jan 2018 18:47:46 -0800 (PST)","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","To":"Paolo Bonzini ,\n\t\"Michael S. Tsirkin\" , =?utf-8?q?Herv=C3=A9_Poussinea?=\n\t=?utf-8?q?u?= ,\n\tAurelien Jarno , Eduardo Habkost\n\t, Marcel Apfelbaum ","Date":"Sun, 7 Jan 2018 23:45:57 -0300","Message-Id":"<20180108024558.17983-29-f4bug@amsat.org>","X-Mailer":"git-send-email 2.15.1","In-Reply-To":"<20180108024558.17983-1-f4bug@amsat.org>","References":"<20180108024558.17983-1-f4bug@amsat.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::241","Subject":"[Qemu-devel] [PATCH 28/29] piix: merge common code from isa/piix4.c\n\twith southbridge piix3","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Igor Mammedov , =?utf-8?q?Philippe_Mathieu-Daud?=\n\t=?utf-8?b?w6k=?= , \tqemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Signed-off-by: Philippe Mathieu-Daudé \n---\n hw/isa/piix4.c | 218 --------------------------------------------\n hw/southbridge/piix.c | 246 +++++++++++++++++++++++++++++++++++++++++---------\n hw/isa/Makefile.objs | 1 -\n 3 files changed, 203 insertions(+), 262 deletions(-)\n delete mode 100644 hw/isa/piix4.c","diff":"diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c\ndeleted file mode 100644\nindex c78516e595..0000000000\n--- a/hw/isa/piix4.c\n+++ /dev/null\n@@ -1,218 +0,0 @@\n-/*\n- * QEMU PIIX4 PCI Bridge Emulation\n- *\n- * Copyright (c) 2006 Fabrice Bellard\n- * Copyright (c) 2018 Hervé Poussineau\n- *\n- * Permission is hereby granted, free of charge, to any person obtaining a copy\n- * of this software and associated documentation files (the \"Software\"), to deal\n- * in the Software without restriction, including without limitation the rights\n- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n- * copies of the Software, and to permit persons to whom the Software is\n- * furnished to do so, subject to the following conditions:\n- *\n- * The above copyright notice and this permission notice shall be included in\n- * all copies or substantial portions of the Software.\n- *\n- * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n- * THE SOFTWARE.\n- */\n-\n-#include \"qemu/osdep.h\"\n-#include \"hw/hw.h\"\n-#include \"hw/i386/pc.h\"\n-#include \"hw/pci/pci.h\"\n-#include \"hw/isa/isa.h\"\n-#include \"hw/southbridge/i82371_piix.h\"\n-#include \"hw/dma/i8257.h\"\n-#include \"hw/sysbus.h\"\n-#include \"hw/audio/pcspk.h\"\n-#include \"hw/timer/i8254.h\"\n-\n-PCIDevice *piix4_dev;\n-\n-typedef struct PIIX4State {\n- PCIDevice dev;\n- qemu_irq cpu_intr;\n- qemu_irq *isa;\n-\n- /* Reset Control Register */\n- MemoryRegion rcr_mem;\n- uint8_t rcr;\n-} PIIX4State;\n-\n-#define TYPE_PIIX4_PCI_DEVICE \"PIIX4\"\n-#define PIIX4_PCI_DEVICE(obj) \\\n- OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)\n-\n-static void piix4_reset(DeviceState *dev)\n-{\n- PIIX4State *s = PIIX4_PCI_DEVICE(dev);\n- uint8_t *pci_conf = s->dev.config;\n-\n- pci_conf[0x04] = 0x07; // master, memory and I/O\n- pci_conf[0x05] = 0x00;\n- pci_conf[0x06] = 0x00;\n- pci_conf[0x07] = 0x02; // PCI_status_devsel_medium\n- pci_conf[0x4c] = 0x4d;\n- pci_conf[0x4e] = 0x03;\n- pci_conf[0x4f] = 0x00;\n- pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10\n- pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10\n- pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11\n- pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11\n- pci_conf[0x69] = 0x02;\n- pci_conf[0x70] = 0x80;\n- pci_conf[0x76] = 0x0c;\n- pci_conf[0x77] = 0x0c;\n- pci_conf[0x78] = 0x02;\n- pci_conf[0x79] = 0x00;\n- pci_conf[0x80] = 0x00;\n- pci_conf[0x82] = 0x00;\n- pci_conf[0xa0] = 0x08;\n- pci_conf[0xa2] = 0x00;\n- pci_conf[0xa3] = 0x00;\n- pci_conf[0xa4] = 0x00;\n- pci_conf[0xa5] = 0x00;\n- pci_conf[0xa6] = 0x00;\n- pci_conf[0xa7] = 0x00;\n- pci_conf[0xa8] = 0x0f;\n- pci_conf[0xaa] = 0x00;\n- pci_conf[0xab] = 0x00;\n- pci_conf[0xac] = 0x00;\n- pci_conf[0xae] = 0x00;\n-}\n-\n-static const VMStateDescription vmstate_piix4 = {\n- .name = \"PIIX4\",\n- .version_id = 2,\n- .minimum_version_id = 2,\n- .fields = (VMStateField[]) {\n- VMSTATE_PCI_DEVICE(dev, PIIX4State),\n- VMSTATE_END_OF_LIST()\n- }\n-};\n-\n-static void piix4_request_i8259_irq(void *opaque, int irq, int level)\n-{\n- PIIX4State *s = opaque;\n- qemu_set_irq(s->cpu_intr, level);\n-}\n-\n-static void piix4_set_i8259_irq(void *opaque, int irq, int level)\n-{\n- PIIX4State *s = opaque;\n- qemu_set_irq(s->isa[irq], level);\n-}\n-\n-static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,\n- unsigned int len)\n-{\n- PIIX4State *s = opaque;\n-\n- if (val & 4) {\n- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);\n- return;\n- }\n- s->rcr = val & 2; /* keep System Reset type only */\n-}\n-\n-static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)\n-{\n- PIIX4State *s = opaque;\n- return s->rcr;\n-}\n-\n-static const MemoryRegionOps piix4_rcr_ops = {\n- .read = piix4_rcr_read,\n- .write = piix4_rcr_write,\n- .endianness = DEVICE_LITTLE_ENDIAN,\n- .impl = {\n- .min_access_size = 1,\n- .max_access_size = 1,\n- },\n-};\n-\n-static void piix4_realize(PCIDevice *pci_dev, Error **errp)\n-{\n- DeviceState *dev = DEVICE(pci_dev);\n- PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);\n- ISABus *isa_bus;\n- ISADevice *pit;\n- qemu_irq *i8259_out_irq;\n-\n- isa_bus = isa_bus_new(dev, pci_address_space(pci_dev),\n- pci_address_space_io(pci_dev), errp);\n- if (!isa_bus) {\n- return;\n- }\n-\n- qdev_init_gpio_in_named(dev, piix4_set_i8259_irq, \"isa\", ISA_NUM_IRQS);\n- qdev_init_gpio_out_named(dev, &s->cpu_intr, \"intr\", 1);\n-\n- memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,\n- \"reset-control\", 1);\n- memory_region_add_subregion_overlap(pci_address_space_io(pci_dev), 0xcf9,\n- &s->rcr_mem, 1);\n-\n- /* initialize i8259 pic */\n- i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);\n- s->isa = i8259_init(isa_bus, *i8259_out_irq);\n-\n- /* initialize ISA irqs */\n- isa_bus_irqs(isa_bus, s->isa);\n-\n- /* initialize pit */\n- pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);\n-\n- /* speaker */\n- pcspk_init(isa_bus, pit);\n-\n- /* DMA */\n- i8257_dma_init(isa_bus, 0);\n-\n- piix4_dev = pci_dev;\n-}\n-\n-static void piix4_class_init(ObjectClass *klass, void *data)\n-{\n- DeviceClass *dc = DEVICE_CLASS(klass);\n- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);\n-\n- k->realize = piix4_realize;\n- k->vendor_id = PCI_VENDOR_ID_INTEL;\n- k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;\n- k->class_id = PCI_CLASS_BRIDGE_ISA;\n- dc->reset = piix4_reset;\n- dc->desc = \"ISA bridge\";\n- dc->vmsd = &vmstate_piix4;\n- /*\n- * Reason: part of PIIX4 southbridge, needs to be wired up,\n- * e.g. by mips_malta_init()\n- */\n- dc->user_creatable = false;\n- dc->hotpluggable = false;\n-}\n-\n-static const TypeInfo piix4_info = {\n- .name = TYPE_PIIX4_PCI_DEVICE,\n- .parent = TYPE_PCI_DEVICE,\n- .instance_size = sizeof(PIIX4State),\n- .class_init = piix4_class_init,\n- .interfaces = (InterfaceInfo[]) {\n- { INTERFACE_CONVENTIONAL_PCI_DEVICE },\n- { },\n- },\n-};\n-\n-static void piix4_register_types(void)\n-{\n- type_register_static(&piix4_info);\n-}\n-\n-type_init(piix4_register_types)\ndiff --git a/hw/southbridge/piix.c b/hw/southbridge/piix.c\nindex 2d429d6b29..53ee177866 100644\n--- a/hw/southbridge/piix.c\n+++ b/hw/southbridge/piix.c\n@@ -24,17 +24,26 @@\n \n #include \"qemu/osdep.h\"\n #include \"qemu/range.h\"\n+#include \"qapi/error.h\"\n #include \"sysemu/sysemu.h\"\n #include \"hw/hw.h\"\n+#include \"hw/i386/pc.h\"\n #include \"hw/southbridge/i82371_piix.h\"\n+#include \"hw/dma/i8257.h\"\n+#include \"hw/audio/pcspk.h\"\n+#include \"hw/timer/i8254.h\"\n #include \"hw/xen/xen.h\"\n \n #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */\n #define XEN_PIIX_NUM_PIRQS 128ULL\n #define PIIX_PIRQC 0x60\n \n-typedef struct PIIX3State {\n+typedef struct PIIXState {\n+ /*< private >*/\n PCIDevice dev;\n+ /*< public >*/\n+\n+ ISABus *isa_bus;\n \n /*\n * bitmap to track pic levels.\n@@ -50,6 +59,7 @@ typedef struct PIIX3State {\n #endif\n uint64_t pic_levels;\n \n+ qemu_irq cpu_intr;\n qemu_irq *pic;\n \n /* This member isn't used. Just for save/load compatibility */\n@@ -57,14 +67,43 @@ typedef struct PIIX3State {\n \n /* Reset Control Register contents */\n uint8_t rcr;\n-\n /* IO memory region for Reset Control Register (RCR_IOPORT) */\n MemoryRegion rcr_mem;\n-} PIIX3State;\n+} PIIXState;\n \n-#define TYPE_PIIX3_PCI_DEVICE \"pci-piix3\"\n-#define PIIX3_PCI_DEVICE(obj) \\\n- OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)\n+static void piix_rcr_write(void *opaque, hwaddr addr, uint64_t val,\n+ unsigned int len)\n+{\n+ PIIXState *s = opaque;\n+\n+ if (val & 4) {\n+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);\n+ return;\n+ }\n+ s->rcr = val & 2; /* keep System Reset type only */\n+}\n+\n+static uint64_t piix_rcr_read(void *opaque, hwaddr addr, unsigned int len)\n+{\n+ PIIXState *s = opaque;\n+ return s->rcr;\n+}\n+\n+static const MemoryRegionOps rcr_ops = {\n+ .read = piix_rcr_read,\n+ .write = piix_rcr_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+ .impl = {\n+ .min_access_size = 1,\n+ .max_access_size = 1,\n+ },\n+};\n+\n+static void piix_rcr_init(PIIXState *s, MemoryRegion *io, const char *regname)\n+{\n+ memory_region_init_io(&s->rcr_mem, OBJECT(s), &rcr_ops, s, regname, 1);\n+ memory_region_add_subregion_overlap(io, RCR_IOPORT, &s->rcr_mem, 1);\n+}\n \n /* return the global irq number corresponding to a given device irq\n pin. We could also use the bus number to have a more precise\n@@ -76,6 +115,28 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)\n return (pci_intx + slot_addend) & 3;\n }\n \n+static void piix_realize(PCIDevice *pci_dev, PIIXState *s, Error **errp)\n+{\n+ MemoryRegion *pci_io = pci_address_space_io(pci_dev);\n+\n+ s->isa_bus = isa_bus_new(DEVICE(s), pci_address_space(pci_dev),\n+ pci_io, errp);\n+ if (!s->isa_bus) {\n+ if (!errp) {\n+ error_setg(errp, \"can not create ISA bus\");\n+ }\n+ return;\n+ }\n+\n+ piix_rcr_init(s, pci_io, \"reset-control\");\n+}\n+\n+typedef struct PIIXState PIIX3State;\n+\n+#define TYPE_PIIX3_PCI_DEVICE \"pci-piix3\"\n+#define PIIX3_PCI_DEVICE(obj) \\\n+ OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)\n+\n /* PIIX3 PCI to ISA bridge */\n static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)\n {\n@@ -314,44 +375,9 @@ static const VMStateDescription vmstate_piix3 = {\n }\n };\n \n-\n-static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)\n-{\n- PIIX3State *d = opaque;\n-\n- if (val & 4) {\n- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);\n- return;\n- }\n- d->rcr = val & 2; /* keep System Reset type only */\n-}\n-\n-static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)\n-{\n- PIIX3State *d = opaque;\n-\n- return d->rcr;\n-}\n-\n-static const MemoryRegionOps rcr_ops = {\n- .read = rcr_read,\n- .write = rcr_write,\n- .endianness = DEVICE_LITTLE_ENDIAN\n-};\n-\n-static void piix3_realize(PCIDevice *dev, Error **errp)\n+static void piix3_realize(PCIDevice *pci_dev, Error **errp)\n {\n- PIIX3State *d = PIIX3_PCI_DEVICE(dev);\n-\n- if (!isa_bus_new(DEVICE(d), get_system_memory(),\n- pci_address_space_io(dev), errp)) {\n- return;\n- }\n-\n- memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,\n- \"piix3-reset-control\", 1);\n- memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,\n- &d->rcr_mem, 1);\n+ piix_realize(pci_dev, PIIX3_PCI_DEVICE(pci_dev), errp);\n }\n \n static void pci_piix3_class_init(ObjectClass *klass, void *data)\n@@ -413,11 +439,145 @@ static const TypeInfo piix3_xen_info = {\n .class_init = piix3_xen_class_init,\n };\n \n+typedef struct PIIXState PIIX4State;\n+\n+#define TYPE_PIIX4_PCI_DEVICE \"PIIX4\"\n+#define PIIX4_PCI_DEVICE(obj) \\\n+ OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)\n+\n+static const VMStateDescription vmstate_piix4 = {\n+ .name = \"PIIX4\",\n+ .version_id = 2,\n+ .minimum_version_id = 2,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_PCI_DEVICE(dev, PIIX4State),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static void piix4_request_i8259_irq(void *opaque, int irq, int level)\n+{\n+ PIIX4State *s = opaque;\n+ qemu_set_irq(s->cpu_intr, level);\n+}\n+\n+static void piix4_set_i8259_irq(void *opaque, int irq, int level)\n+{\n+ PIIX4State *s = opaque;\n+ qemu_set_irq(s->pic[irq], level);\n+}\n+\n+static void piix4_reset(DeviceState *dev)\n+{\n+ PIIX4State *s = PIIX4_PCI_DEVICE(dev);\n+ uint8_t *pci_conf = s->dev.config;\n+\n+ pci_conf[0x04] = 0x07; /* master, memory and I/O */\n+ pci_conf[0x05] = 0x00;\n+ pci_conf[0x06] = 0x00;\n+ pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */\n+ pci_conf[0x4c] = 0x4d;\n+ pci_conf[0x4e] = 0x03;\n+ pci_conf[0x4f] = 0x00;\n+ pci_conf[0x60] = 0x0a; /* PCI A -> IRQ 10 */\n+ pci_conf[0x61] = 0x0a; /* PCI B -> IRQ 10 */\n+ pci_conf[0x62] = 0x0b; /* PCI C -> IRQ 11 */\n+ pci_conf[0x63] = 0x0b; /* PCI D -> IRQ 11 */\n+ pci_conf[0x69] = 0x02;\n+ pci_conf[0x70] = 0x80;\n+ pci_conf[0x76] = 0x0c;\n+ pci_conf[0x77] = 0x0c;\n+ pci_conf[0x78] = 0x02;\n+ pci_conf[0x79] = 0x00;\n+ pci_conf[0x80] = 0x00;\n+ pci_conf[0x82] = 0x00;\n+ pci_conf[0xa0] = 0x08;\n+ pci_conf[0xa2] = 0x00;\n+ pci_conf[0xa3] = 0x00;\n+ pci_conf[0xa4] = 0x00;\n+ pci_conf[0xa5] = 0x00;\n+ pci_conf[0xa6] = 0x00;\n+ pci_conf[0xa7] = 0x00;\n+ pci_conf[0xa8] = 0x0f;\n+ pci_conf[0xaa] = 0x00;\n+ pci_conf[0xab] = 0x00;\n+ pci_conf[0xac] = 0x00;\n+ pci_conf[0xae] = 0x00;\n+}\n+\n+PCIDevice *piix4_dev;\n+\n+static void piix4_realize(PCIDevice *pci_dev, Error **errp)\n+{\n+ DeviceState *dev = DEVICE(pci_dev);\n+ PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev);\n+ ISADevice *pit;\n+ qemu_irq *i8259_out_irq;\n+\n+ piix_realize(pci_dev, s, errp);\n+ if (errp) {\n+ return;\n+ }\n+\n+ qdev_init_gpio_in_named(dev, piix4_set_i8259_irq, \"isa\", ISA_NUM_IRQS);\n+ qdev_init_gpio_out_named(dev, &s->cpu_intr, \"intr\", 1);\n+\n+ /* initialize i8259 pic */\n+ i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);\n+ s->pic = i8259_init(s->isa_bus, *i8259_out_irq);\n+\n+ /* initialize ISA irqs */\n+ isa_bus_irqs(s->isa_bus, s->pic);\n+\n+ /* initialize pit */\n+ pit = i8254_pit_init(s->isa_bus, 0x40, 0, NULL);\n+\n+ /* speaker */\n+ pcspk_init(s->isa_bus, pit);\n+\n+ /* DMA */\n+ i8257_dma_init(s->isa_bus, 0);\n+\n+ piix4_dev = pci_dev;\n+}\n+\n+static void piix4_class_init(ObjectClass *klass, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);\n+\n+ k->realize = piix4_realize;\n+ k->vendor_id = PCI_VENDOR_ID_INTEL;\n+ k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;\n+ k->class_id = PCI_CLASS_BRIDGE_ISA;\n+ dc->reset = piix4_reset;\n+ dc->desc = \"ISA bridge\";\n+ dc->vmsd = &vmstate_piix4;\n+ /*\n+ * Reason: part of PIIX4 southbridge, needs to be wired up,\n+ * e.g. by mips_malta_init()\n+ */\n+ dc->user_creatable = false;\n+ dc->hotpluggable = false;\n+}\n+\n+static const TypeInfo piix4_info = {\n+ .name = TYPE_PIIX4_PCI_DEVICE,\n+ .parent = TYPE_PCI_DEVICE,\n+ .instance_size = sizeof(PIIX4State),\n+ .class_init = piix4_class_init,\n+ .interfaces = (InterfaceInfo[]) {\n+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },\n+ { },\n+ },\n+};\n+\n static void piix_register_types(void)\n {\n type_register_static(&piix3_pci_type_info);\n type_register_static(&piix3_info);\n type_register_static(&piix3_xen_info);\n+ type_register_static(&piix4_info);\n }\n \n type_init(piix_register_types)\ndiff --git a/hw/isa/Makefile.objs b/hw/isa/Makefile.objs\nindex fa071082d4..40c34ba184 100644\n--- a/hw/isa/Makefile.objs\n+++ b/hw/isa/Makefile.objs\n@@ -3,7 +3,6 @@ common-obj-$(CONFIG_ISA_BUS) += isa-superio.o\n common-obj-$(CONFIG_APM) += apm.o\n common-obj-$(CONFIG_I82378) += i82378.o\n common-obj-$(CONFIG_PC87312) += pc87312.o\n-common-obj-$(CONFIG_PCI_PIIX) += piix4.o\n common-obj-$(CONFIG_VT82C686) += vt82c686.o\n \n obj-$(CONFIG_LPC_ICH9) += lpc_ich9.o\n","prefixes":["28/29"]}