{"id":856671,"url":"http://patchwork.ozlabs.org/api/patches/856671/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20180108024558.17983-23-f4bug@amsat.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20180108024558.17983-23-f4bug@amsat.org>","list_archive_url":null,"date":"2018-01-08T02:45:51","name":"[22/29] piix3: extract piix3_init() from i440fx_init()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"01106cb414291a3f728a05f114d293506b17761e","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/?format=json","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20180108024558.17983-23-f4bug@amsat.org/mbox/","series":[{"id":21847,"url":"http://patchwork.ozlabs.org/api/series/21847/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=21847","date":"2018-01-08T02:45:30","name":"remove i386/pc dependency: generic SuperIO, PIIX cleanup","version":1,"mbox":"http://patchwork.ozlabs.org/series/21847/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/856671/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/856671/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Tsirkin\" , =?utf-8?q?Herv=C3=A9_Poussinea?=\n\t=?utf-8?q?u?= ,\n\tAurelien Jarno , Eduardo Habkost\n\t, Marcel Apfelbaum ","Date":"Sun, 7 Jan 2018 23:45:51 -0300","Message-Id":"<20180108024558.17983-23-f4bug@amsat.org>","X-Mailer":"git-send-email 2.15.1","In-Reply-To":"<20180108024558.17983-1-f4bug@amsat.org>","References":"<20180108024558.17983-1-f4bug@amsat.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::242","Subject":"[Qemu-devel] [PATCH 22/29] piix3: extract piix3_init() from\n\ti440fx_init()","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Igor Mammedov , =?utf-8?q?Philippe_Mathieu-Daud?=\n\t=?utf-8?b?w6k=?= , \tqemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Signed-off-by: Philippe Mathieu-Daudé \n---\n include/hw/southbridge/i82371_piix.h | 4 +++\n hw/pci-host/piix.c | 62 ++++++++++++++++++++----------------\n 2 files changed, 38 insertions(+), 28 deletions(-)","diff":"diff --git a/include/hw/southbridge/i82371_piix.h b/include/hw/southbridge/i82371_piix.h\nindex 8a5f9a7596..00a9f4d5b9 100644\n--- a/include/hw/southbridge/i82371_piix.h\n+++ b/include/hw/southbridge/i82371_piix.h\n@@ -22,6 +22,10 @@\n */\n #define RCR_IOPORT 0xcf9\n \n+/* piix.c */\n+PCIDevice *piix3_init(PCIBus *bus, ISABus **isa_bus,\n+ qemu_irq *pic, int *piix3_devfn);\n+\n /* piix4.c */\n extern PCIDevice *piix4_dev;\n \ndiff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c\nindex 0bd22fa33a..6e8cea8372 100644\n--- a/hw/pci-host/piix.c\n+++ b/hw/pci-host/piix.c\n@@ -27,6 +27,7 @@\n #include \"hw/i386/pc.h\"\n #include \"hw/pci/pci.h\"\n #include \"hw/pci/pci_host.h\"\n+#include \"hw/southbridge/i82371_piix.h\"\n #include \"hw/isa/isa.h\"\n #include \"hw/sysbus.h\"\n #include \"qapi/error.h\"\n@@ -120,11 +121,6 @@ struct PCII440FXState {\n */\n #define I440FX_COREBOOT_RAM_SIZE 0x57\n \n-static void piix3_set_irq(void *opaque, int pirq, int level);\n-static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);\n-static void piix3_write_config_xen(PCIDevice *dev,\n- uint32_t address, uint32_t val, int len);\n-\n /* return the global irq number corresponding to a given device irq\n pin. We could also use the bus number to have a more precise\n mapping. */\n@@ -353,7 +349,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,\n PCIBus *b;\n PCIDevice *d;\n PCIHostState *s;\n- PIIX3State *piix3;\n PCII440FXState *f;\n unsigned i;\n I440FXState *i440fx;\n@@ -406,28 +401,7 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,\n PAM_EXPAN_SIZE);\n }\n \n- /* Xen supports additional interrupt routes from the PCI devices to\n- * the IOAPIC: the four pins of each PCI device on the bus are also\n- * connected to the IOAPIC directly.\n- * These additional routes can be discovered through ACPI. */\n- if (xen_enabled()) {\n- PCIDevice *pci_dev = pci_create_simple_multifunction(b,\n- -1, true, \"PIIX3-xen\");\n- piix3 = PIIX3_PCI_DEVICE(pci_dev);\n- pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,\n- piix3, XEN_PIIX_NUM_PIRQS);\n- } else {\n- PCIDevice *pci_dev = pci_create_simple_multifunction(b,\n- -1, true, \"PIIX3\");\n- piix3 = PIIX3_PCI_DEVICE(pci_dev);\n- pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,\n- PIIX_NUM_PIRQS);\n- pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);\n- }\n- piix3->pic = pic;\n- *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), \"isa.0\"));\n-\n- *piix3_devfn = piix3->dev.devfn;\n+ piix3_init(b, isa_bus, pic, piix3_devfn);\n \n ram_size = ram_size / 8 / 1024 / 1024;\n if (ram_size > 255) {\n@@ -508,6 +482,38 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)\n return route;\n }\n \n+PCIDevice *piix3_init(PCIBus *bus, ISABus **isa_bus,\n+ qemu_irq *pic, int *piix3_devfn)\n+{\n+ PCIDevice *pci_dev;\n+ PIIX3State *piix3;\n+\n+ /* Xen supports additional interrupt routes from the PCI devices to\n+ * the IOAPIC: the four pins of each PCI device on the bus are also\n+ * connected to the IOAPIC directly.\n+ * These additional routes can be discovered through ACPI. */\n+ if (xen_enabled()) {\n+ pci_dev = pci_create_simple_multifunction(bus,\n+ -1, true, \"PIIX3-xen\");\n+ piix3 = PIIX3_PCI_DEVICE(pci_dev);\n+ pci_bus_irqs(bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,\n+ piix3, XEN_PIIX_NUM_PIRQS);\n+ } else {\n+ pci_dev = pci_create_simple_multifunction(bus,\n+ -1, true, \"PIIX3\");\n+ piix3 = PIIX3_PCI_DEVICE(pci_dev);\n+ pci_bus_irqs(bus, piix3_set_irq, pci_slot_get_pirq, piix3,\n+ PIIX_NUM_PIRQS);\n+ pci_bus_set_route_irq_fn(bus, piix3_route_intx_pin_to_irq);\n+ }\n+ piix3->pic = pic;\n+ *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), \"isa.0\"));\n+\n+ *piix3_devfn = piix3->dev.devfn;\n+\n+ return pci_dev;\n+}\n+\n /* irq routing is changed. so rebuild bitmap */\n static void piix3_update_irq_levels(PIIX3State *piix3)\n {\n","prefixes":["22/29"]}