{"id":819576,"url":"http://patchwork.ozlabs.org/api/patches/819576/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20170928125044.32516-2-mperttunen@nvidia.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170928125044.32516-2-mperttunen@nvidia.com>","list_archive_url":null,"date":"2017-09-28T12:50:39","name":"[v3,1/6] gpu: host1x: Enable Tegra186 syncpoint protection","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"17a9f9b3931ee310c9c0eb9ae3036fbf11bc9e82","submitter":{"id":26499,"url":"http://patchwork.ozlabs.org/api/people/26499/?format=json","name":"Mikko Perttunen","email":"mperttunen@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20170928125044.32516-2-mperttunen@nvidia.com/mbox/","series":[{"id":5559,"url":"http://patchwork.ozlabs.org/api/series/5559/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=5559","date":"2017-09-28T12:50:44","name":"Miscellaneous improvements to Host1x and TegraDRM","version":3,"mbox":"http://patchwork.ozlabs.org/series/5559/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/819576/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/819576/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tsecure) header.d=kapsi.fi header.i=@kapsi.fi header.b=\"XcQFo7Zl\";\n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2vk54yx7z9t3B\n\tfor ;\n\tThu, 28 Sep 2017 22:53:01 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753214AbdI1Mwe (ORCPT );\n\tThu, 28 Sep 2017 08:52:34 -0400","from mail.kapsi.fi ([91.232.154.25]:59917 \"EHLO mail.kapsi.fi\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1752962AbdI1Mv4 (ORCPT );\n\tThu, 28 Sep 2017 08:51:56 -0400","from dsl-hkibng22-54f983-249.dhcp.inet.fi ([84.249.131.249]\n\thelo=localhost.localdomain) by mail.kapsi.fi with esmtpsa\n\t(TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dxYIB-0007ES-OH; Thu, 28 Sep 2017 15:51:51 +0300"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kapsi.fi;\n\ts=20161220; \n\th=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From;\n\tbh=VuMgWEhD397ptNamJaA3/eiDKHA3ycxlGUQPV5lJV9k=; \n\tb=XcQFo7ZltxthIU580d3NaAEgGfws7Qao30a/QczIagKQdZjIR05pi7UaIrt3AcYkKjdpb106UKW2yjFmn3y9X9gDATkW7MEgf1gF+IIAXSdSjbH5I5CU+ZjbxAKHYRU+Kptqh2TXmBPSyMCouPw+2ldfPQ83WtShmudEMtqIzyj3RhoFxeIR+07OleVCAVUAuXnolQWp7LgnOk/4LASHPgbOsbaNpSalRmf2KrOlO+9tSTIoZTgtMXCnM6M5WwKP4JkrOGx0w7FTBjMKNvrkJA92xU9kfpNct4D3FtRMCB1uCS9iXJBL8BiFg8ULFtieMQw2jrjhi6Ua4uB1Ttbh1A==;","From":"Mikko Perttunen ","To":"thierry.reding@gmail.com, jonathanh@nvidia.com","Cc":"digetx@gmail.com, dri-devel@lists.freedesktop.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tMikko Perttunen ","Subject":"[PATCH v3 1/6] gpu: host1x: Enable Tegra186 syncpoint protection","Date":"Thu, 28 Sep 2017 15:50:39 +0300","Message-Id":"<20170928125044.32516-2-mperttunen@nvidia.com>","X-Mailer":"git-send-email 2.14.1","In-Reply-To":"<20170928125044.32516-1-mperttunen@nvidia.com>","References":"<20170928125044.32516-1-mperttunen@nvidia.com>","X-SA-Exim-Connect-IP":"84.249.131.249","X-SA-Exim-Mail-From":"mperttunen@nvidia.com","X-SA-Exim-Scanned":"No (on mail.kapsi.fi); SAEximRunCond expanded to false","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-tegra@vger.kernel.org"},"content":"Since Tegra186 the Host1x hardware allows syncpoints to be assigned to\nspecific channels, preventing any other channels from incrementing\nthem.\n\nEnable this feature where available and assign syncpoints to channels\nwhen submitting a job. Syncpoints are currently never unassigned from\nchannels since that would require extra work and is unnecessary with\nthe current channel allocation model.\n\nSigned-off-by: Mikko Perttunen \n---\n drivers/gpu/host1x/dev.h | 15 +++++++++++++\n drivers/gpu/host1x/hw/channel_hw.c | 3 +++\n drivers/gpu/host1x/hw/syncpt_hw.c | 46 ++++++++++++++++++++++++++++++++++++++\n drivers/gpu/host1x/syncpt.c | 8 +++++++\n 4 files changed, 72 insertions(+)","diff":"diff --git a/drivers/gpu/host1x/dev.h b/drivers/gpu/host1x/dev.h\nindex def802c0a6bf..502769726480 100644\n--- a/drivers/gpu/host1x/dev.h\n+++ b/drivers/gpu/host1x/dev.h\n@@ -79,6 +79,9 @@ struct host1x_syncpt_ops {\n \tu32 (*load)(struct host1x_syncpt *syncpt);\n \tint (*cpu_incr)(struct host1x_syncpt *syncpt);\n \tint (*patch_wait)(struct host1x_syncpt *syncpt, void *patch_addr);\n+\tvoid (*assign_to_channel)(struct host1x_syncpt *syncpt,\n+\t struct host1x_channel *channel);\n+\tvoid (*enable_protection)(struct host1x *host);\n };\n \n struct host1x_intr_ops {\n@@ -186,6 +189,18 @@ static inline int host1x_hw_syncpt_patch_wait(struct host1x *host,\n \treturn host->syncpt_op->patch_wait(sp, patch_addr);\n }\n \n+static inline void host1x_hw_syncpt_assign_to_channel(\n+\tstruct host1x *host, struct host1x_syncpt *sp,\n+\tstruct host1x_channel *ch)\n+{\n+\treturn host->syncpt_op->assign_to_channel(sp, ch);\n+}\n+\n+static inline void host1x_hw_syncpt_enable_protection(struct host1x *host)\n+{\n+\treturn host->syncpt_op->enable_protection(host);\n+}\n+\n static inline int host1x_hw_intr_init_host_sync(struct host1x *host, u32 cpm,\n \t\t\tvoid (*syncpt_thresh_work)(struct work_struct *))\n {\ndiff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c\nindex 8447a56c41ca..b929d7f1e291 100644\n--- a/drivers/gpu/host1x/hw/channel_hw.c\n+++ b/drivers/gpu/host1x/hw/channel_hw.c\n@@ -147,6 +147,9 @@ static int channel_submit(struct host1x_job *job)\n \n \tsyncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);\n \n+\t/* assign syncpoint to channel */\n+\thost1x_hw_syncpt_assign_to_channel(host, sp, ch);\n+\n \tjob->syncpt_end = syncval;\n \n \t/* add a setclass for modules that require it */\ndiff --git a/drivers/gpu/host1x/hw/syncpt_hw.c b/drivers/gpu/host1x/hw/syncpt_hw.c\nindex 7b0270d60742..7dfd47d74f89 100644\n--- a/drivers/gpu/host1x/hw/syncpt_hw.c\n+++ b/drivers/gpu/host1x/hw/syncpt_hw.c\n@@ -106,6 +106,50 @@ static int syncpt_patch_wait(struct host1x_syncpt *sp, void *patch_addr)\n \treturn 0;\n }\n \n+/**\n+ * syncpt_assign_to_channel() - Assign syncpoint to channel\n+ * @sp: syncpoint\n+ * @ch: channel\n+ *\n+ * On chips with the syncpoint protection feature (Tegra186+), assign @sp to\n+ * @ch, preventing other channels from incrementing the syncpoints. If @ch is\n+ * NULL, unassigns the syncpoint.\n+ *\n+ * On older chips, do nothing.\n+ */\n+static void syncpt_assign_to_channel(struct host1x_syncpt *sp,\n+\t\t\t\t struct host1x_channel *ch)\n+{\n+#if HOST1X_HW >= 6\n+\tstruct host1x *host = sp->host;\n+\n+\tif (!host->hv_regs)\n+\t\treturn;\n+\n+\thost1x_sync_writel(host,\n+\t\t\t HOST1X_SYNC_SYNCPT_CH_APP_CH(ch ? ch->id : 0xff),\n+\t\t\t HOST1X_SYNC_SYNCPT_CH_APP(sp->id));\n+#endif\n+}\n+\n+/**\n+ * syncpt_enable_protection() - Enable syncpoint protection\n+ * @host: host1x instance\n+ *\n+ * On chips with the syncpoint protection feature (Tegra186+), enable this\n+ * feature. On older chips, do nothing.\n+ */\n+static void syncpt_enable_protection(struct host1x *host)\n+{\n+#if HOST1X_HW >= 6\n+\tif (!host->hv_regs)\n+\t\treturn;\n+\n+\thost1x_hypervisor_writel(host, HOST1X_HV_SYNCPT_PROT_EN_CH_EN,\n+\t\t\t\t HOST1X_HV_SYNCPT_PROT_EN);\n+#endif\n+}\n+\n static const struct host1x_syncpt_ops host1x_syncpt_ops = {\n \t.restore = syncpt_restore,\n \t.restore_wait_base = syncpt_restore_wait_base,\n@@ -113,4 +157,6 @@ static const struct host1x_syncpt_ops host1x_syncpt_ops = {\n \t.load = syncpt_load,\n \t.cpu_incr = syncpt_cpu_incr,\n \t.patch_wait = syncpt_patch_wait,\n+\t.assign_to_channel = syncpt_assign_to_channel,\n+\t.enable_protection = syncpt_enable_protection,\n };\ndiff --git a/drivers/gpu/host1x/syncpt.c b/drivers/gpu/host1x/syncpt.c\nindex 048ac9e344ce..bce7cd6db724 100644\n--- a/drivers/gpu/host1x/syncpt.c\n+++ b/drivers/gpu/host1x/syncpt.c\n@@ -398,6 +398,13 @@ int host1x_syncpt_init(struct host1x *host)\n \tfor (i = 0; i < host->info->nb_pts; i++) {\n \t\tsyncpt[i].id = i;\n \t\tsyncpt[i].host = host;\n+\n+\t\t/*\n+\t\t * Unassign syncpt from channels for purposes of Tegra186\n+\t\t * syncpoint protection. This prevents any channel from\n+\t\t * accessing it until it is reassigned.\n+\t\t */\n+\t\thost1x_hw_syncpt_assign_to_channel(host, &syncpt[i], NULL);\n \t}\n \n \tfor (i = 0; i < host->info->nb_bases; i++)\n@@ -408,6 +415,7 @@ int host1x_syncpt_init(struct host1x *host)\n \thost->bases = bases;\n \n \thost1x_syncpt_restore(host);\n+\thost1x_hw_syncpt_enable_protection(host);\n \n \t/* Allocate sync point to use for clearing waits for expired fences */\n \thost->nop_sp = host1x_syncpt_alloc(host, NULL, 0);\n","prefixes":["v3","1/6"]}