{"id":819574,"url":"http://patchwork.ozlabs.org/api/patches/819574/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20170928125044.32516-5-mperttunen@nvidia.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170928125044.32516-5-mperttunen@nvidia.com>","list_archive_url":null,"date":"2017-09-28T12:50:42","name":"[v3,4/6] gpu: host1x: Disassemble more instructions","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"4be3cf6ca1d440347a50257f1af75f220a49c257","submitter":{"id":26499,"url":"http://patchwork.ozlabs.org/api/people/26499/?format=json","name":"Mikko Perttunen","email":"mperttunen@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20170928125044.32516-5-mperttunen@nvidia.com/mbox/","series":[{"id":5559,"url":"http://patchwork.ozlabs.org/api/series/5559/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=5559","date":"2017-09-28T12:50:44","name":"Miscellaneous improvements to Host1x and TegraDRM","version":3,"mbox":"http://patchwork.ozlabs.org/series/5559/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/819574/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/819574/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tsecure) header.d=kapsi.fi header.i=@kapsi.fi header.b=\"ockbZuO9\";\n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2vjZ5Y2kz9t3B\n\tfor ;\n\tThu, 28 Sep 2017 22:52:34 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752782AbdI1MwV (ORCPT );\n\tThu, 28 Sep 2017 08:52:21 -0400","from mail.kapsi.fi ([91.232.154.25]:39808 \"EHLO mail.kapsi.fi\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1753131AbdI1Mv5 (ORCPT );\n\tThu, 28 Sep 2017 08:51:57 -0400","from dsl-hkibng22-54f983-249.dhcp.inet.fi ([84.249.131.249]\n\thelo=localhost.localdomain) by mail.kapsi.fi with esmtpsa\n\t(TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dxYIC-0007ES-12; Thu, 28 Sep 2017 15:51:52 +0300"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kapsi.fi;\n\ts=20161220; \n\th=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From;\n\tbh=ZmVqqFLCF5GTjS24qHJkGbwvz6sCqdEWnMmc921Brik=; \n\tb=ockbZuO9Lx4JUa5o1ozYAD7MCNIBUGqTkb1eB+fOBiHWaKtoCN8e7+c+xujKS+5mZcaCIH35T/sos4sCSj0obnZI7mJEqwWqP4jjCH8vd5QieZ7m7hmyaOwAsHSTuiSUjzBfIoHBa98wAhtTOBGXhcR6rM+gCel2n7LEcqsUeXp2kyyXVK/d9CV8K/K53bB2wqJCLUptFQDVq/cX7HhfRZrtmjTr7TOF09mA8Iua0sd6juPVBPzOYAfbbbUghAc0ZgkzEI+/8iZciH6yQCNvhBotKkvIDg23d3bUhN993FbwuC0PHRJ9DGdKrFfpA4C7jfKWy4kRvffZPsEgkJoEFA==;","From":"Mikko Perttunen ","To":"thierry.reding@gmail.com, jonathanh@nvidia.com","Cc":"digetx@gmail.com, dri-devel@lists.freedesktop.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tMikko Perttunen ","Subject":"[PATCH v3 4/6] gpu: host1x: Disassemble more instructions","Date":"Thu, 28 Sep 2017 15:50:42 +0300","Message-Id":"<20170928125044.32516-5-mperttunen@nvidia.com>","X-Mailer":"git-send-email 2.14.1","In-Reply-To":"<20170928125044.32516-1-mperttunen@nvidia.com>","References":"<20170928125044.32516-1-mperttunen@nvidia.com>","X-SA-Exim-Connect-IP":"84.249.131.249","X-SA-Exim-Mail-From":"mperttunen@nvidia.com","X-SA-Exim-Scanned":"No (on mail.kapsi.fi); SAEximRunCond expanded to false","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-tegra@vger.kernel.org"},"content":"The disassembler for debug dumps was missing some newer host1x opcodes.\nAdd disassembly support for these.\n\nSigned-off-by: Mikko Perttunen \n---\n drivers/gpu/host1x/hw/debug_hw.c | 59 ++++++++++++++++++++++++++++++++---\n drivers/gpu/host1x/hw/debug_hw_1x01.c | 2 +-\n drivers/gpu/host1x/hw/debug_hw_1x06.c | 3 +-\n 3 files changed, 58 insertions(+), 6 deletions(-)","diff":"diff --git a/drivers/gpu/host1x/hw/debug_hw.c b/drivers/gpu/host1x/hw/debug_hw.c\nindex 1e67667e308c..989476801f9d 100644\n--- a/drivers/gpu/host1x/hw/debug_hw.c\n+++ b/drivers/gpu/host1x/hw/debug_hw.c\n@@ -30,6 +30,13 @@ enum {\n \tHOST1X_OPCODE_IMM\t= 0x04,\n \tHOST1X_OPCODE_RESTART\t= 0x05,\n \tHOST1X_OPCODE_GATHER\t= 0x06,\n+\tHOST1X_OPCODE_SETSTRMID = 0x07,\n+\tHOST1X_OPCODE_SETAPPID = 0x08,\n+\tHOST1X_OPCODE_SETPYLD = 0x09,\n+\tHOST1X_OPCODE_INCR_W = 0x0a,\n+\tHOST1X_OPCODE_NONINCR_W = 0x0b,\n+\tHOST1X_OPCODE_GATHER_W = 0x0c,\n+\tHOST1X_OPCODE_RESTART_W = 0x0d,\n \tHOST1X_OPCODE_EXTEND\t= 0x0e,\n };\n \n@@ -38,11 +45,16 @@ enum {\n \tHOST1X_OPCODE_EXTEND_RELEASE_MLOCK\t= 0x01,\n };\n \n-static unsigned int show_channel_command(struct output *o, u32 val)\n+#define INVALID_PAYLOAD\t\t\t\t0xffffffff\n+\n+static unsigned int show_channel_command(struct output *o, u32 val,\n+\t\t\t\t\t u32 *payload)\n {\n-\tunsigned int mask, subop, num;\n+\tunsigned int mask, subop, num, opcode;\n+\n+\topcode = val >> 28;\n \n-\tswitch (val >> 28) {\n+\tswitch (opcode) {\n \tcase HOST1X_OPCODE_SETCLASS:\n \t\tmask = val & 0x3f;\n \t\tif (mask) {\n@@ -97,6 +109,44 @@ static unsigned int show_channel_command(struct output *o, u32 val)\n \t\t\t\t val >> 14 & 0x1, val & 0x3fff);\n \t\treturn 1;\n \n+#if HOST1X_HW >= 6\n+\tcase HOST1X_OPCODE_SETSTRMID:\n+\t\thost1x_debug_cont(o, \"SETSTRMID(offset=%06x)\\n\",\n+\t\t\t\t val & 0x3fffff);\n+\t\treturn 0;\n+\n+\tcase HOST1X_OPCODE_SETAPPID:\n+\t\thost1x_debug_cont(o, \"SETAPPID(appid=%02x)\\n\", val & 0xff);\n+\t\treturn 0;\n+\n+\tcase HOST1X_OPCODE_SETPYLD:\n+\t\t*payload = val & 0xffff;\n+\t\thost1x_debug_cont(o, \"SETPYLD(data=%04x)\\n\", *payload);\n+\t\treturn 0;\n+\n+\tcase HOST1X_OPCODE_INCR_W:\n+\tcase HOST1X_OPCODE_NONINCR_W:\n+\t\thost1x_debug_cont(o, \"%s(offset=%06x, \",\n+\t\t\t\t opcode == HOST1X_OPCODE_INCR_W ?\n+\t\t\t\t\t\"INCR_W\" : \"NONINCR_W\",\n+\t\t\t\t val & 0x3fffff);\n+\t\tif (*payload == 0) {\n+\t\t\thost1x_debug_cont(o, \"[])\\n\");\n+\t\t\treturn 0;\n+\t\t} else if (*payload == INVALID_PAYLOAD) {\n+\t\t\thost1x_debug_cont(o, \"unknown)\\n\");\n+\t\t\treturn 0;\n+\t\t} else {\n+\t\t\thost1x_debug_cont(o, \"[\");\n+\t\t\treturn *payload;\n+\t\t}\n+\n+\tcase HOST1X_OPCODE_GATHER_W:\n+\t\thost1x_debug_cont(o, \"GATHER_W(count=%04x, addr=[\",\n+\t\t\t\t val & 0x3fff);\n+\t\treturn 2;\n+#endif\n+\n \tcase HOST1X_OPCODE_EXTEND:\n \t\tsubop = val >> 24 & 0xf;\n \t\tif (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK)\n@@ -122,6 +172,7 @@ static void show_gather(struct output *o, phys_addr_t phys_addr,\n \t/* Map dmaget cursor to corresponding mem handle */\n \tu32 offset = phys_addr - pin_addr;\n \tunsigned int data_count = 0, i;\n+\tu32 payload = INVALID_PAYLOAD;\n \n \t/*\n \t * Sometimes we're given different hardware address to the same\n@@ -139,7 +190,7 @@ static void show_gather(struct output *o, phys_addr_t phys_addr,\n \n \t\tif (!data_count) {\n \t\t\thost1x_debug_output(o, \"%08x: %08x: \", addr, val);\n-\t\t\tdata_count = show_channel_command(o, val);\n+\t\t\tdata_count = show_channel_command(o, val, &payload);\n \t\t} else {\n \t\t\thost1x_debug_cont(o, \"%08x%s\", val,\n \t\t\t\t\t data_count > 1 ? \", \" : \"])\\n\");\ndiff --git a/drivers/gpu/host1x/hw/debug_hw_1x01.c b/drivers/gpu/host1x/hw/debug_hw_1x01.c\nindex 09e1aa7bb5dd..8790d5fd5f20 100644\n--- a/drivers/gpu/host1x/hw/debug_hw_1x01.c\n+++ b/drivers/gpu/host1x/hw/debug_hw_1x01.c\n@@ -112,7 +112,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,\n \n \t\tif (!data_count) {\n \t\t\thost1x_debug_output(o, \"%08x: \", val);\n-\t\t\tdata_count = show_channel_command(o, val);\n+\t\t\tdata_count = show_channel_command(o, val, NULL);\n \t\t} else {\n \t\t\thost1x_debug_cont(o, \"%08x%s\", val,\n \t\t\t\t\t data_count > 1 ? \", \" : \"])\\n\");\ndiff --git a/drivers/gpu/host1x/hw/debug_hw_1x06.c b/drivers/gpu/host1x/hw/debug_hw_1x06.c\nindex bd89da5dc64c..b503c740c022 100644\n--- a/drivers/gpu/host1x/hw/debug_hw_1x06.c\n+++ b/drivers/gpu/host1x/hw/debug_hw_1x06.c\n@@ -63,6 +63,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,\n \t\t\t\t\t struct output *o)\n {\n \tu32 val, rd_ptr, wr_ptr, start, end;\n+\tu32 payload = INVALID_PAYLOAD;\n \tunsigned int data_count = 0;\n \n \thost1x_debug_output(o, \"%u: fifo:\\n\", ch->id);\n@@ -107,7 +108,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,\n \t\tif (!data_count) {\n \t\t\thost1x_debug_output(o, \"%03x 0x%08x: \",\n \t\t\t\t\t rd_ptr - start, val);\n-\t\t\tdata_count = show_channel_command(o, val);\n+\t\t\tdata_count = show_channel_command(o, val, &payload);\n \t\t} else {\n \t\t\thost1x_debug_cont(o, \"%08x%s\", val,\n \t\t\t\t\t data_count > 1 ? \", \" : \"])\\n\");\n","prefixes":["v3","4/6"]}