{"id":819515,"url":"http://patchwork.ozlabs.org/api/patches/819515/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20170928095628.21966-5-thierry.reding@gmail.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170928095628.21966-5-thierry.reding@gmail.com>","list_archive_url":null,"date":"2017-09-28T09:56:16","name":"[v2,04/16] gpio: Move irq_base to struct gpio_irq_chip","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"56ee0d2e2a22d1a23a2afcdddf06a4eeb80dc50a","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/?format=json","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20170928095628.21966-5-thierry.reding@gmail.com/mbox/","series":[{"id":5529,"url":"http://patchwork.ozlabs.org/api/series/5529/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=5529","date":"2017-09-28T09:56:12","name":"gpio: Tight IRQ chip integration and banked infrastructure","version":2,"mbox":"http://patchwork.ozlabs.org/series/5529/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/819515/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/819515/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=w+DhwV9t2NgFE3N7LI7HewAfrMuZ+0l9GuUIOqMTUgU=;\n\tb=WYV5W2ptGy+Mq4a7o3Zf0Ham40QYIg/NcVcL+3HaQ7lbkJOKbCzxbDI8uE5vTZNJ6z\n\t2OgLs5p1TaIhdUxXcjFUd+7SvLvM4PW5GDfUfHIb0rKQQOJR6atEOQSLyV4wPNICDbKx\n\tsF9zLbo3rvom51VSgk45yZgfiY7y3sgX0ESJ+Bnz772M5kKDw5wIBkYHFdashpt3/Kxb\n\t8RmGeMXGBKBt3T+LozoD24nr9OvS4zCYN4GOQiMB/Dyo1/PHLMH7r8B6q8G3QiLmnQRN\n\tNQVmhEU7zHatjUOWVaDqpeUU9djDyJsMKHn643sctc1ssdgtXZVXZ9Zclwc/IlaAiyzb\n\tFmfA==","X-Gm-Message-State":"AHPjjUhXmcaeT1Z5zuCwxCJe6Wqs7rOzm3LIwhoA0fJXQsUctQWI6dJg\n\t7sl+KJsNplV1YHnx/p+aN28=","X-Google-Smtp-Source":"AOwi7QBqne1S9LzC6ULX3CTbQoEZyKP7VkYhLXjGBVvThzW07k03dpoZXQhSSQ65IV20pGAHapFB2A==","X-Received":"by 10.55.43.226 with SMTP id r95mr6262549qkr.0.1506592603312;\n\tThu, 28 Sep 2017 02:56:43 -0700 (PDT)","From":"Thierry Reding ","To":"Linus Walleij ","Cc":"Jonathan Hunter , linux-gpio@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org","Subject":"[PATCH v2 04/16] gpio: Move irq_base to struct gpio_irq_chip","Date":"Thu, 28 Sep 2017 11:56:16 +0200","Message-Id":"<20170928095628.21966-5-thierry.reding@gmail.com>","X-Mailer":"git-send-email 2.14.1","In-Reply-To":"<20170928095628.21966-1-thierry.reding@gmail.com>","References":"<20170928095628.21966-1-thierry.reding@gmail.com>","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"},"content":"From: Thierry Reding \n\nIn order to consolidate the multiple ways to associate an IRQ chip with\na GPIO chip, move more fields into the new struct gpio_irq_chip.\n\nSigned-off-by: Thierry Reding \n---\n drivers/gpio/gpiolib.c | 2 +-\n drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 2 +-\n include/linux/gpio/driver.h | 10 ++++++++--\n 3 files changed, 10 insertions(+), 4 deletions(-)","diff":"diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c\nindex f4e18e0ffb56..2f0fa3d646d2 100644\n--- a/drivers/gpio/gpiolib.c\n+++ b/drivers/gpio/gpiolib.c\n@@ -1770,7 +1770,7 @@ static int gpiochip_add_irqchip(struct gpio_chip *gpiochip)\n \t\tops = &gpiochip_domain_ops;\n \n \tgpiochip->irq.domain = irq_domain_add_simple(np, gpiochip->ngpio,\n-\t\t\t\t\t\t gpiochip->irq_base,\n+\t\t\t\t\t\t gpiochip->irq.first,\n \t\t\t\t\t\t ops, gpiochip);\n \tif (!gpiochip->irq.domain)\n \t\treturn -EINVAL;\ndiff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c\nindex c9851bd120b4..500238d898ea 100644\n--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c\n+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c\n@@ -627,7 +627,7 @@ static void armada_37xx_irq_handler(struct irq_desc *desc)\n static unsigned int armada_37xx_irq_startup(struct irq_data *d)\n {\n \tstruct gpio_chip *chip = irq_data_get_irq_chip_data(d);\n-\tint irq = d->hwirq - chip->irq_base;\n+\tint irq = d->hwirq - chip->irq.first;\n \t/*\n \t * The mask field is a \"precomputed bitmask for accessing the\n \t * chip registers\" which was introduced for the generic\ndiff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h\nindex 031037bb8670..9389406df0b1 100644\n--- a/include/linux/gpio/driver.h\n+++ b/include/linux/gpio/driver.h\n@@ -46,6 +46,14 @@ struct gpio_irq_chip {\n \t */\n \tconst struct irq_domain_ops *domain_ops;\n \n+\t/**\n+\t * @first:\n+\t *\n+\t * If not dynamically assigned, the base (first) IRQ to allocate GPIO\n+\t * chip IRQs from (deprecated).\n+\t */\n+\tunsigned int first;\n+\n \t/**\n \t * @parent_handler:\n \t *\n@@ -152,7 +160,6 @@ static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)\n *\tsafely.\n * @bgpio_dir: shadowed direction register for generic GPIO to clear/set\n *\tdirection safely.\n- * @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated)\n * @irq_handler: the irq handler to use (often a predefined irq core function)\n *\tfor GPIO IRQs, provided by GPIO driver\n * @irq_default_type: default IRQ triggering type applied during GPIO driver\n@@ -232,7 +239,6 @@ struct gpio_chip {\n \t * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib\n \t * to handle IRQs for most practical cases.\n \t */\n-\tunsigned int\t\tirq_base;\n \tirq_flow_handler_t\tirq_handler;\n \tunsigned int\t\tirq_default_type;\n \tunsigned int\t\tirq_chained_parent;\n","prefixes":["v2","04/16"]}