{"id":819438,"url":"http://patchwork.ozlabs.org/api/patches/819438/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-aspeed/patch/20170928075149.8154-8-joel@jms.id.au/","project":{"id":57,"url":"http://patchwork.ozlabs.org/api/projects/57/?format=json","name":"Linux ASPEED SoC development","link_name":"linux-aspeed","list_id":"linux-aspeed.lists.ozlabs.org","list_email":"linux-aspeed@lists.ozlabs.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170928075149.8154-8-joel@jms.id.au>","list_archive_url":null,"date":"2017-09-28T07:51:48","name":"[7/8] ARM: dts: aspeed: Add aliases for UARTs","commit_ref":null,"pull_url":null,"state":"superseded","archived":true,"hash":"9e42093fa10cc60eb09525ee7ae584fc92652914","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/people/48628/?format=json","name":"Joel Stanley","email":"joel@jms.id.au"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-aspeed/patch/20170928075149.8154-8-joel@jms.id.au/mbox/","series":[{"id":5506,"url":"http://patchwork.ozlabs.org/api/series/5506/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-aspeed/list/?series=5506","date":"2017-09-28T07:51:41","name":"ARM: dts: aspeed: Device tree updates","version":1,"mbox":"http://patchwork.ozlabs.org/series/5506/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/819438/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/819438/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","linux-aspeed@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","linux-aspeed@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2n4J1kBhz9t66\n\tfor ;\n\tThu, 28 Sep 2017 17:53:20 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3y2n4H6rl0zDsPp\n\tfor ;\n\tThu, 28 Sep 2017 17:53:19 +1000 (AEST)","from mail-pg0-x241.google.com (mail-pg0-x241.google.com\n\t[IPv6:2607:f8b0:400e:c05::241])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3y2n4F1fRyzDsPp\n\tfor ;\n\tThu, 28 Sep 2017 17:53:17 +1000 (AEST)","by mail-pg0-x241.google.com with SMTP id d8so1067031pgt.3\n\tfor ;\n\tThu, 28 Sep 2017 00:53:17 -0700 (PDT)","from aurora.jms.id.au ([203.0.153.9])\n\tby smtp.gmail.com with ESMTPSA id\n\tt8sm1586841pfh.116.2017.09.28.00.53.08\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 28 Sep 2017 00:53:13 -0700 (PDT)","by aurora.jms.id.au (sSMTP sendmail emulation);\n\tThu, 28 Sep 2017 17:23:06 +0930"],"Authentication-Results":["ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"Wtcma9pe\"; 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To\nensure the UARTs show up where users expect them, we give them fixed\naliases starting at 0.\n\nSigned-off-by: Joel Stanley \n---\n arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 4 ----\n arch/arm/boot/dts/aspeed-g4.dtsi | 5 +++++\n arch/arm/boot/dts/aspeed-g5.dtsi | 5 +++++\n 3 files changed, 10 insertions(+), 4 deletions(-)","diff":"diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts\nindex e387c80b7f4f..be51be5a5f39 100644\n--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts\n+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts\n@@ -6,10 +6,6 @@\n \tmodel = \"Palmetto BMC\";\n \tcompatible = \"tyan,palmetto-bmc\", \"aspeed,ast2400\";\n \n-\taliases {\n-\t\tserial4 = &uart5;\n-\t};\n-\n \tchosen {\n \t\tstdout-path = &uart5;\n \t\tbootargs = \"console=ttyS4,115200 earlyprintk\";\ndiff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi\nindex f8611d5a6465..191c33d18122 100644\n--- a/arch/arm/boot/dts/aspeed-g4.dtsi\n+++ b/arch/arm/boot/dts/aspeed-g4.dtsi\n@@ -22,6 +22,11 @@\n \t\ti2c11 = &i2c11;\n \t\ti2c12 = &i2c12;\n \t\ti2c13 = &i2c13;\n+\t\tserial0 = &uart1;\n+\t\tserial1 = &uart2;\n+\t\tserial2 = &uart3;\n+\t\tserial3 = &uart4;\n+\t\tserial4 = &uart5;\n \t};\n \n \tcpus {\ndiff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi\nindex de127370131d..251fc9f4637e 100644\n--- a/arch/arm/boot/dts/aspeed-g5.dtsi\n+++ b/arch/arm/boot/dts/aspeed-g5.dtsi\n@@ -22,6 +22,11 @@\n \t\ti2c11 = &i2c11;\n \t\ti2c12 = &i2c12;\n \t\ti2c13 = &i2c13;\n+\t\tserial0 = &uart1;\n+\t\tserial1 = &uart2;\n+\t\tserial2 = &uart3;\n+\t\tserial3 = &uart4;\n+\t\tserial4 = &uart5;\n \t};\n \n \tcpus {\n","prefixes":["7/8"]}