{"id":819400,"url":"http://patchwork.ozlabs.org/api/patches/819400/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/patch/20170928044132.30940-3-saeedm@mellanox.com/","project":{"id":7,"url":"http://patchwork.ozlabs.org/api/projects/7/?format=json","name":"Linux network development","link_name":"netdev","list_id":"netdev.vger.kernel.org","list_email":"netdev@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170928044132.30940-3-saeedm@mellanox.com>","list_archive_url":null,"date":"2017-09-28T04:41:23","name":"[net,02/11] net/mlx5: Fix FPGA capability location","commit_ref":null,"pull_url":null,"state":"accepted","archived":true,"hash":"e6a27402c172760a223866a4cb35cd94e9c127f8","submitter":{"id":65299,"url":"http://patchwork.ozlabs.org/api/people/65299/?format=json","name":"Saeed Mahameed","email":"saeedm@mellanox.com"},"delegate":{"id":34,"url":"http://patchwork.ozlabs.org/api/users/34/?format=json","username":"davem","first_name":"David","last_name":"Miller","email":"davem@davemloft.net"},"mbox":"http://patchwork.ozlabs.org/project/netdev/patch/20170928044132.30940-3-saeedm@mellanox.com/mbox/","series":[{"id":5488,"url":"http://patchwork.ozlabs.org/api/series/5488/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/list/?series=5488","date":"2017-09-28T04:41:23","name":"Mellanox, mlx5 fixes 2017-09-28","version":1,"mbox":"http://patchwork.ozlabs.org/series/5488/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/819400/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/819400/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2hqh3LZ6z9tXb\n\tfor ;\n\tThu, 28 Sep 2017 14:42:08 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751830AbdI1EmG (ORCPT );\n\tThu, 28 Sep 2017 00:42:06 -0400","from mail-il-dmz.mellanox.com ([193.47.165.129]:54346 \"EHLO\n\tmellanox.co.il\" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org\n\twith ESMTP id S1750935AbdI1EmE (ORCPT\n\t); Thu, 28 Sep 2017 00:42:04 -0400","from Internal Mail-Server by MTLPINE1 (envelope-from\n\tsaeedm@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 28 Sep 2017 06:42:01 +0200","from sws.mtl.labs.mlnx (reg-l-vrt-045-015.mtl.labs.mlnx\n\t[10.135.45.15])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id v8S4g1j6011096;\n\tThu, 28 Sep 2017 07:42:01 +0300"],"From":"Saeed Mahameed ","To":"\"David S. Miller\" ","Cc":"netdev@vger.kernel.org, Inbar Karmy ,\n\tSaeed Mahameed ","Subject":"[net 02/11] net/mlx5: Fix FPGA capability location","Date":"Thu, 28 Sep 2017 07:41:23 +0300","Message-Id":"<20170928044132.30940-3-saeedm@mellanox.com>","X-Mailer":"git-send-email 2.13.0","In-Reply-To":"<20170928044132.30940-1-saeedm@mellanox.com>","References":"<20170928044132.30940-1-saeedm@mellanox.com>","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"},"content":"From: Inbar Karmy \n\nCurrently, FPGA capability is located in (mdev)->caps.hca_cur,\nchange the location to be (mdev)->caps.fpga,\nsince hca_cur is reserved for HCA device capabilities.\n\nFixes: e29341fb3a5b (\"net/mlx5: FPGA, Add basic support for Innova\")\nSigned-off-by: Inbar Karmy \nSigned-off-by: Saeed Mahameed \n---\n drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.c | 4 ++--\n drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h | 2 +-\n drivers/net/ethernet/mellanox/mlx5/core/fpga/core.c | 3 +--\n include/linux/mlx5/device.h | 5 ++---\n include/linux/mlx5/driver.h | 1 +\n 5 files changed, 7 insertions(+), 8 deletions(-)","diff":"diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.c\nindex e37453d838db..c0fd2212e890 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.c\n@@ -71,11 +71,11 @@ int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,\n \treturn 0;\n }\n \n-int mlx5_fpga_caps(struct mlx5_core_dev *dev, u32 *caps)\n+int mlx5_fpga_caps(struct mlx5_core_dev *dev)\n {\n \tu32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};\n \n-\treturn mlx5_core_access_reg(dev, in, sizeof(in), caps,\n+\treturn mlx5_core_access_reg(dev, in, sizeof(in), dev->caps.fpga,\n \t\t\t\t MLX5_ST_SZ_BYTES(fpga_cap),\n \t\t\t\t MLX5_REG_FPGA_CAP, 0, 0);\n }\ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h b/drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h\nindex 94bdfd47c3f0..d05233c9b4f6 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h\n@@ -65,7 +65,7 @@ struct mlx5_fpga_qp_counters {\n \tu64 rx_total_drop;\n };\n \n-int mlx5_fpga_caps(struct mlx5_core_dev *dev, u32 *caps);\n+int mlx5_fpga_caps(struct mlx5_core_dev *dev);\n int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query);\n int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op);\n int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,\ndiff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/core.c b/drivers/net/ethernet/mellanox/mlx5/core/fpga/core.c\nindex 9034e9960a76..dc8970346521 100644\n--- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/core.c\n+++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/core.c\n@@ -139,8 +139,7 @@ int mlx5_fpga_device_start(struct mlx5_core_dev *mdev)\n \tif (err)\n \t\tgoto out;\n \n-\terr = mlx5_fpga_caps(fdev->mdev,\n-\t\t\t fdev->mdev->caps.hca_cur[MLX5_CAP_FPGA]);\n+\terr = mlx5_fpga_caps(fdev->mdev);\n \tif (err)\n \t\tgoto out;\n \ndiff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h\nindex eaf4ad209c8f..e32dbc4934db 100644\n--- a/include/linux/mlx5/device.h\n+++ b/include/linux/mlx5/device.h\n@@ -980,7 +980,6 @@ enum mlx5_cap_type {\n \tMLX5_CAP_RESERVED,\n \tMLX5_CAP_VECTOR_CALC,\n \tMLX5_CAP_QOS,\n-\tMLX5_CAP_FPGA,\n \t/* NUM OF CAP Types */\n \tMLX5_CAP_NUM\n };\n@@ -1110,10 +1109,10 @@ enum mlx5_mcam_feature_groups {\n \tMLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)\n \n #define MLX5_CAP_FPGA(mdev, cap) \\\n-\tMLX5_GET(fpga_cap, (mdev)->caps.hca_cur[MLX5_CAP_FPGA], cap)\n+\tMLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)\n \n #define MLX5_CAP64_FPGA(mdev, cap) \\\n-\tMLX5_GET64(fpga_cap, (mdev)->caps.hca_cur[MLX5_CAP_FPGA], cap)\n+\tMLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)\n \n enum {\n \tMLX5_CMD_STAT_OK\t\t\t= 0x0,\ndiff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h\nindex 02ff700e4f30..401c8972cc3a 100644\n--- a/include/linux/mlx5/driver.h\n+++ b/include/linux/mlx5/driver.h\n@@ -774,6 +774,7 @@ struct mlx5_core_dev {\n \t\tu32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];\n \t\tu32 pcam[MLX5_ST_SZ_DW(pcam_reg)];\n \t\tu32 mcam[MLX5_ST_SZ_DW(mcam_reg)];\n+\t\tu32 fpga[MLX5_ST_SZ_DW(fpga_cap)];\n \t} caps;\n \tphys_addr_t\t\tiseg_base;\n \tstruct mlx5_init_seg __iomem *iseg;\n","prefixes":["net","02/11"]}