{"id":819289,"url":"http://patchwork.ozlabs.org/api/patches/819289/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170927195635.16014-4-ehabkost@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170927195635.16014-4-ehabkost@redhat.com>","list_archive_url":null,"date":"2017-09-27T19:56:33","name":"[v2,3/5] pci: Add INTERFACE_PCIE_DEVICE to all PCIe devices","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"5f350b9c8d7f8077e254e1428d8b2734f5202fcc","submitter":{"id":195,"url":"http://patchwork.ozlabs.org/api/people/195/?format=json","name":"Eduardo Habkost","email":"ehabkost@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170927195635.16014-4-ehabkost@redhat.com/mbox/","series":[{"id":5434,"url":"http://patchwork.ozlabs.org/api/series/5434/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=5434","date":"2017-09-27T19:56:30","name":"Mark conventional/PCIe/hybrid PCI devices using interface names","version":2,"mbox":"http://patchwork.ozlabs.org/series/5434/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/819289/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/819289/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=ehabkost@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2TCL0JXZz9t30\n\tfor ;\n\tThu, 28 Sep 2017 05:58:22 +1000 (AEST)","from localhost ([::1]:56152 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dxITM-0006mk-59\n\tfor incoming@patchwork.ozlabs.org; Wed, 27 Sep 2017 15:58:20 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:47540)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dxISU-0006e2-Mx\n\tfor qemu-devel@nongnu.org; Wed, 27 Sep 2017 15:57:27 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dxIST-0007Lc-Hl\n\tfor qemu-devel@nongnu.org; Wed, 27 Sep 2017 15:57:26 -0400","from mx1.redhat.com ([209.132.183.28]:58438)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dxISO-0007JC-Ja; Wed, 27 Sep 2017 15:57:20 -0400","from smtp.corp.redhat.com\n\t(int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 7D76ABA1F6;\n\tWed, 27 Sep 2017 19:57:19 +0000 (UTC)","from localhost (ovpn-116-18.gru2.redhat.com [10.97.116.18])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id DDB3389D3D;\n\tWed, 27 Sep 2017 19:57:11 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 7D76ABA1F6","From":"Eduardo Habkost ","To":"qemu-devel@nongnu.org","Date":"Wed, 27 Sep 2017 16:56:33 -0300","Message-Id":"<20170927195635.16014-4-ehabkost@redhat.com>","In-Reply-To":"<20170927195635.16014-1-ehabkost@redhat.com>","References":"<20170927195635.16014-1-ehabkost@redhat.com>","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.16","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.25]);\n\tWed, 27 Sep 2017 19:57:19 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"[Qemu-devel] [PATCH v2 3/5] pci: Add INTERFACE_PCIE_DEVICE to all\n\tPCIe devices","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Kevin Wolf , Hannes Reinecke ,\n\tqemu-block@nongnu.org, Paul Burton ,\n\t\"Michael S. Tsirkin\" ,\n\tJason Wang , Max Reitz ,\n\tKeith Busch ,\n\tDmitry Fleytman , \n\tAlex Williamson ,\n\tPaolo Bonzini , Laine Stump , \n\tAlistair Francis ,\n\tMarcel Apfelbaum , David Gibson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Change all devices that set is_express=1 to implement\nINTERFACE_PCIE_DEVICE.\n\nCc: Keith Busch \nCc: Kevin Wolf \nCc: Max Reitz \nCc: Dmitry Fleytman \nCc: Jason Wang \nCc: \"Michael S. Tsirkin\" \nCc: Marcel Apfelbaum \nCc: Paul Burton \nCc: Paolo Bonzini \nCc: Hannes Reinecke \nCc: qemu-block@nongnu.org\nReviewed-by: Alistair Francis \nSigned-off-by: Eduardo Habkost \n---\nChanges v1 -> v2:\n* base-xhci is marked as hybrid, now (in another patch)\n* Included pcie-pci-bridge\n---\n hw/block/nvme.c | 4 ++++\n hw/net/e1000e.c | 4 ++++\n hw/pci-bridge/pcie_pci_bridge.c | 1 +\n hw/pci-bridge/pcie_root_port.c | 4 ++++\n hw/pci-bridge/xio3130_downstream.c | 4 ++++\n hw/pci-bridge/xio3130_upstream.c | 4 ++++\n hw/pci-host/xilinx-pcie.c | 4 ++++\n hw/scsi/megasas.c | 6 ++++++\n 8 files changed, 31 insertions(+)","diff":"diff --git a/hw/block/nvme.c b/hw/block/nvme.c\nindex 9aa32692a3..441e21ed1f 100644\n--- a/hw/block/nvme.c\n+++ b/hw/block/nvme.c\n@@ -1110,6 +1110,10 @@ static const TypeInfo nvme_info = {\n .instance_size = sizeof(NvmeCtrl),\n .class_init = nvme_class_init,\n .instance_init = nvme_instance_init,\n+ .interfaces = (InterfaceInfo[]) {\n+ { INTERFACE_PCIE_DEVICE },\n+ { }\n+ },\n };\n \n static void nvme_register_types(void)\ndiff --git a/hw/net/e1000e.c b/hw/net/e1000e.c\nindex 6c42b4478c..81f7934a59 100644\n--- a/hw/net/e1000e.c\n+++ b/hw/net/e1000e.c\n@@ -708,6 +708,10 @@ static const TypeInfo e1000e_info = {\n .instance_size = sizeof(E1000EState),\n .class_init = e1000e_class_init,\n .instance_init = e1000e_instance_init,\n+ .interfaces = (InterfaceInfo[]) {\n+ { INTERFACE_PCIE_DEVICE },\n+ { }\n+ },\n };\n \n static void e1000e_register_types(void)\ndiff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c\nindex 9aa5cc3e45..88db143633 100644\n--- a/hw/pci-bridge/pcie_pci_bridge.c\n+++ b/hw/pci-bridge/pcie_pci_bridge.c\n@@ -180,6 +180,7 @@ static const TypeInfo pcie_pci_bridge_info = {\n .class_init = pcie_pci_bridge_class_init,\n .interfaces = (InterfaceInfo[]) {\n { TYPE_HOTPLUG_HANDLER },\n+ { INTERFACE_PCIE_DEVICE },\n { },\n }\n };\ndiff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c\nindex 4d588cb22e..9b6e4ce512 100644\n--- a/hw/pci-bridge/pcie_root_port.c\n+++ b/hw/pci-bridge/pcie_root_port.c\n@@ -161,6 +161,10 @@ static const TypeInfo rp_info = {\n .class_init = rp_class_init,\n .abstract = true,\n .class_size = sizeof(PCIERootPortClass),\n+ .interfaces = (InterfaceInfo[]) {\n+ { INTERFACE_PCIE_DEVICE },\n+ { }\n+ },\n };\n \n static void rp_register_types(void)\ndiff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c\nindex e706f36cb7..7d2f7629c1 100644\n--- a/hw/pci-bridge/xio3130_downstream.c\n+++ b/hw/pci-bridge/xio3130_downstream.c\n@@ -195,6 +195,10 @@ static const TypeInfo xio3130_downstream_info = {\n .name = \"xio3130-downstream\",\n .parent = TYPE_PCIE_SLOT,\n .class_init = xio3130_downstream_class_init,\n+ .interfaces = (InterfaceInfo[]) {\n+ { INTERFACE_PCIE_DEVICE },\n+ { }\n+ },\n };\n \n static void xio3130_downstream_register_types(void)\ndiff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c\nindex a052224bbf..227997ce46 100644\n--- a/hw/pci-bridge/xio3130_upstream.c\n+++ b/hw/pci-bridge/xio3130_upstream.c\n@@ -166,6 +166,10 @@ static const TypeInfo xio3130_upstream_info = {\n .name = \"x3130-upstream\",\n .parent = TYPE_PCIE_PORT,\n .class_init = xio3130_upstream_class_init,\n+ .interfaces = (InterfaceInfo[]) {\n+ { INTERFACE_PCIE_DEVICE },\n+ { }\n+ },\n };\n \n static void xio3130_upstream_register_types(void)\ndiff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c\nindex 4613dda1d2..7659253090 100644\n--- a/hw/pci-host/xilinx-pcie.c\n+++ b/hw/pci-host/xilinx-pcie.c\n@@ -317,6 +317,10 @@ static const TypeInfo xilinx_pcie_root_info = {\n .parent = TYPE_PCI_BRIDGE,\n .instance_size = sizeof(XilinxPCIERoot),\n .class_init = xilinx_pcie_root_class_init,\n+ .interfaces = (InterfaceInfo[]) {\n+ { INTERFACE_PCIE_DEVICE },\n+ { }\n+ },\n };\n \n static void xilinx_pcie_register(void)\ndiff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c\nindex 0db68aacee..535ee267c3 100644\n--- a/hw/scsi/megasas.c\n+++ b/hw/scsi/megasas.c\n@@ -2451,6 +2451,7 @@ typedef struct MegasasInfo {\n int osts;\n const VMStateDescription *vmsd;\n Property *props;\n+ InterfaceInfo *interfaces;\n } MegasasInfo;\n \n static struct MegasasInfo megasas_devices[] = {\n@@ -2480,6 +2481,10 @@ static struct MegasasInfo megasas_devices[] = {\n .is_express = true,\n .vmsd = &vmstate_megasas_gen2,\n .props = megasas_properties_gen2,\n+ .interfaces = (InterfaceInfo[]) {\n+ { INTERFACE_PCIE_DEVICE },\n+ { }\n+ },\n }\n };\n \n@@ -2531,6 +2536,7 @@ static void megasas_register_types(void)\n type_info.parent = TYPE_MEGASAS_BASE;\n type_info.class_data = (void *)info;\n type_info.class_init = megasas_class_init;\n+ type_info.interfaces = info->interfaces;\n \n type_register(&type_info);\n }\n","prefixes":["v2","3/5"]}