{"id":819250,"url":"http://patchwork.ozlabs.org/api/patches/819250/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506533594-9741-2-git-send-email-chakra.divi@openedev.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506533594-9741-2-git-send-email-chakra.divi@openedev.com>","list_archive_url":null,"date":"2017-09-27T17:33:10","name":"[U-Boot,v2,1/5] armv7: Move L2CTLR read/write to common","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"08aa035fe23fdf121fb075ec024d88e8510b6eb6","submitter":{"id":71741,"url":"http://patchwork.ozlabs.org/api/people/71741/?format=json","name":"Chakra Divi","email":"2chakrass@gmail.com"},"delegate":{"id":69486,"url":"http://patchwork.ozlabs.org/api/users/69486/?format=json","username":"ptomsich","first_name":"Philipp","last_name":"Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506533594-9741-2-git-send-email-chakra.divi@openedev.com/mbox/","series":[{"id":5413,"url":"http://patchwork.ozlabs.org/api/series/5413/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=5413","date":"2017-09-27T17:33:09","name":"rk3288: Falcon mode support","version":2,"mbox":"http://patchwork.ozlabs.org/series/5413/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/819250/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/819250/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Jagan Teki \n\nL2CTLR read/write functions are common to armv7 so, move\nthem in to include/asm/armv7.h and use them where ever it need.\n\nCc: Tom Warren \nSigned-off-by: Jagan Teki \n---\nChanges for v2:\n- New patch\n\n arch/arm/include/asm/armv7.h | 21 +++++++++++++++++++++\n arch/arm/mach-rockchip/rk3288-board-spl.c | 22 +---------------------\n arch/arm/mach-tegra/cache.c | 5 +++--\n 3 files changed, 25 insertions(+), 23 deletions(-)","diff":"diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h\nindex a20702e..efc515e 100644\n--- a/arch/arm/include/asm/armv7.h\n+++ b/arch/arm/include/asm/armv7.h\n@@ -61,6 +61,27 @@\n #include \n #include \n \n+/* read L2 control register (L2CTLR) */\n+static inline uint32_t read_l2ctlr(void)\n+{\n+\tuint32_t val = 0;\n+\n+\tasm volatile (\"mrc p15, 1, %0, c9, c0, 2\" : \"=r\" (val));\n+\n+\treturn val;\n+}\n+\n+/* write L2 control register (L2CTLR) */\n+static inline void write_l2ctlr(uint32_t val)\n+{\n+\t/*\n+\t * Note: L2CTLR can only be written when the L2 memory system\n+\t * is idle, ie before the MMU is enabled.\n+\t */\n+\tasm volatile(\"mcr p15, 1, %0, c9, c0, 2\" : : \"r\" (val) : \"memory\");\n+\tisb();\n+}\n+\n /*\n * Workaround for ARM errata # 798870\n * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been\ndiff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c\nindex 6b7bf85..8a1066c 100644\n--- a/arch/arm/mach-rockchip/rk3288-board-spl.c\n+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c\n@@ -13,6 +13,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -80,27 +81,6 @@ u32 spl_boot_mode(const u32 boot_device)\n \treturn MMCSD_MODE_RAW;\n }\n \n-/* read L2 control register (L2CTLR) */\n-static inline uint32_t read_l2ctlr(void)\n-{\n-\tuint32_t val = 0;\n-\n-\tasm volatile (\"mrc p15, 1, %0, c9, c0, 2\" : \"=r\" (val));\n-\n-\treturn val;\n-}\n-\n-/* write L2 control register (L2CTLR) */\n-static inline void write_l2ctlr(uint32_t val)\n-{\n-\t/*\n-\t * Note: L2CTLR can only be written when the L2 memory system\n-\t * is idle, ie before the MMU is enabled.\n-\t */\n-\tasm volatile(\"mcr p15, 1, %0, c9, c0, 2\" : : \"r\" (val) : \"memory\");\n-\tisb();\n-}\n-\n static void configure_l2ctlr(void)\n {\n \tuint32_t l2ctlr;\ndiff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c\nindex 6dad403..2f3f822 100644\n--- a/arch/arm/mach-tegra/cache.c\n+++ b/arch/arm/mach-tegra/cache.c\n@@ -7,6 +7,7 @@\n /* Tegra cache routines */\n \n #include \n+#include \n #include \n #include \n #include \n@@ -30,9 +31,9 @@ void config_cache(void)\n \t * Systems with an architectural L2 cache must not use the PL310.\n \t * Config L2CTLR here for a data RAM latency of 3 cycles.\n \t */\n-\tasm(\"mrc p15, 1, %0, c9, c0, 2\" : : \"r\" (reg));\n+\treg = read_l2ctlr();\n \treg &= ~7;\n \treg |= 2;\n-\tasm(\"mcr p15, 1, %0, c9, c0, 2\" : : \"r\" (reg));\n+\twrite_l2ctlr(reg);\n }\n #endif\n","prefixes":["U-Boot","v2","1/5"]}