{"id":819249,"url":"http://patchwork.ozlabs.org/api/patches/819249/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506533594-9741-3-git-send-email-chakra.divi@openedev.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506533594-9741-3-git-send-email-chakra.divi@openedev.com>","list_archive_url":null,"date":"2017-09-27T17:33:11","name":"[U-Boot,v2,2/5] armv7: rk3288: Move configure_l2ctlr to common","commit_ref":"a982d5156db0587f5118a118c7e9f18d4c70891d","pull_url":null,"state":"accepted","archived":false,"hash":"a37ac9cd3c6b6ac7d7e1263509c6bd045a82f4d0","submitter":{"id":71741,"url":"http://patchwork.ozlabs.org/api/people/71741/?format=json","name":"Chakra Divi","email":"2chakrass@gmail.com"},"delegate":{"id":69486,"url":"http://patchwork.ozlabs.org/api/users/69486/?format=json","username":"ptomsich","first_name":"Philipp","last_name":"Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506533594-9741-3-git-send-email-chakra.divi@openedev.com/mbox/","series":[{"id":5413,"url":"http://patchwork.ozlabs.org/api/series/5413/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=5413","date":"2017-09-27T17:33:09","name":"rk3288: Falcon mode support","version":2,"mbox":"http://patchwork.ozlabs.org/series/5413/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/819249/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/819249/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Jagan Teki \n\nconfigure_l2ctlr will be shared between SPL and TPL so\nmove them into asm/arch/sys_proto.h\n\nSigned-off-by: Jagan Teki \n---\nChanges for v2:\n- New patch\n\n arch/arm/include/asm/arch-rockchip/sys_proto.h | 23 +++++++++++++++++++++++\n arch/arm/mach-rockchip/rk3288-board-spl.c | 21 +--------------------\n 2 files changed, 24 insertions(+), 20 deletions(-)","diff":"diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h\nindex 35423e1..e428d59 100644\n--- a/arch/arm/include/asm/arch-rockchip/sys_proto.h\n+++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h\n@@ -7,4 +7,27 @@\n #ifndef _ASM_ARCH_SYS_PROTO_H\n #define _ASM_ARCH_SYS_PROTO_H\n \n+#ifdef CONFIG_ROCKCHIP_RK3288\n+#include \n+\n+static void configure_l2ctlr(void)\n+{\n+\tuint32_t l2ctlr;\n+\n+\tl2ctlr = read_l2ctlr();\n+\tl2ctlr &= 0xfffc0000; /* clear bit0~bit17 */\n+\n+\t/*\n+\t* Data RAM write latency: 2 cycles\n+\t* Data RAM read latency: 2 cycles\n+\t* Data RAM setup latency: 1 cycle\n+\t* Tag RAM write latency: 1 cycle\n+\t* Tag RAM read latency: 1 cycle\n+\t* Tag RAM setup latency: 1 cycle\n+\t*/\n+\tl2ctlr |= (1 << 3 | 1 << 0);\n+\twrite_l2ctlr(l2ctlr);\n+}\n+#endif /* CONFIG_ROCKCHIP_RK3288 */\n+\n #endif /* _ASM_ARCH_SYS_PROTO_H */\ndiff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c\nindex 8a1066c..23af653 100644\n--- a/arch/arm/mach-rockchip/rk3288-board-spl.c\n+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c\n@@ -13,7 +13,6 @@\n #include \n #include \n #include \n-#include \n #include \n #include \n #include \n@@ -21,6 +20,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -81,25 +81,6 @@ u32 spl_boot_mode(const u32 boot_device)\n \treturn MMCSD_MODE_RAW;\n }\n \n-static void configure_l2ctlr(void)\n-{\n-\tuint32_t l2ctlr;\n-\n-\tl2ctlr = read_l2ctlr();\n-\tl2ctlr &= 0xfffc0000; /* clear bit0~bit17 */\n-\n-\t/*\n-\t* Data RAM write latency: 2 cycles\n-\t* Data RAM read latency: 2 cycles\n-\t* Data RAM setup latency: 1 cycle\n-\t* Tag RAM write latency: 1 cycle\n-\t* Tag RAM read latency: 1 cycle\n-\t* Tag RAM setup latency: 1 cycle\n-\t*/\n-\tl2ctlr |= (1 << 3 | 1 << 0);\n-\twrite_l2ctlr(l2ctlr);\n-}\n-\n #ifdef CONFIG_SPL_MMC_SUPPORT\n static int configure_emmc(struct udevice *pinctrl)\n {\n","prefixes":["U-Boot","v2","2/5"]}