{"id":819131,"url":"http://patchwork.ozlabs.org/api/patches/819131/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506515969-1472-5-git-send-email-kever.yang@rock-chips.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506515969-1472-5-git-send-email-kever.yang@rock-chips.com>","list_archive_url":null,"date":"2017-09-27T12:39:25","name":"[U-Boot,4/8] rockchip: rk3128: add pinctrl driver","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"963c6d2a9a74a20891f069910a06801ef4408608","submitter":{"id":64532,"url":"http://patchwork.ozlabs.org/api/people/64532/?format=json","name":"Kever Yang","email":"kever.yang@rock-chips.com"},"delegate":{"id":69486,"url":"http://patchwork.ozlabs.org/api/users/69486/?format=json","username":"ptomsich","first_name":"Philipp","last_name":"Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506515969-1472-5-git-send-email-kever.yang@rock-chips.com/mbox/","series":[{"id":5353,"url":"http://patchwork.ozlabs.org/api/series/5353/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=5353","date":"2017-09-27T12:39:21","name":"rockchip: add new SoC support for RK3128","version":1,"mbox":"http://patchwork.ozlabs.org/series/5353/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/819131/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/819131/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"oO3Ur2e7\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2HXk3H3Tz9tXf\n\tfor ;\n\tWed, 27 Sep 2017 22:42:46 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 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tests=RCVD_IN_DNSWL_NONE,\n\tRCVD_IN_MSPIKE_H2,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=nMCi4daSH5Jh3FHs73D/clIKtpksIJNnXBUoB9kP0FA=;\n\tb=oO3Ur2e7CmWc8BN0kD7As2D36EaQLw5355MTkisgPrVMKYXC4fnmJ9vxC5U7UOsZYY\n\tFyWJOCXkJacO0dpY43ERWMXtB0fduMIQKc7CiDrCJdV5Cf9y+r6UN0yfuAKm5QZxATpl\n\tPQmetsGa7+XGTktX5EwN3XXEdr3VEOfIHtSyvBWeEOUZFYHtFJalclc67U7S5s5wAYKt\n\tlJQUqDz9HVAKelEfA/IjaqpPNf+AE7kiCncC91glPPhyVcunp8LfFvVufKm/q+o3snXJ\n\tkGMJFEdB4n2HMnEw/ZbNnd/uYxeBmq8gKEPlPU1Dw5Cdu1ztiOU/lTJBYwu4zoO1H9qM\n\twiZQ==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; 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+0800","Message-Id":"<1506515969-1472-5-git-send-email-kever.yang@rock-chips.com>","X-Mailer":"git-send-email 1.9.1","In-Reply-To":"<1506515969-1472-1-git-send-email-kever.yang@rock-chips.com>","References":"<1506515969-1472-1-git-send-email-kever.yang@rock-chips.com>","Cc":"Andy Yan ,\n\tWilliam Zhang ","Subject":"[U-Boot] [PATCH 4/8] rockchip: rk3128: add pinctrl driver","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"Add rk3128 pinctrl driver and grf/iomux structure definition.\n\nSigned-off-by: Kever Yang \n---\n\n arch/arm/include/asm/arch-rockchip/grf_rk3128.h | 551 ++++++++++++++++++++++++\n drivers/pinctrl/Kconfig | 10 +\n drivers/pinctrl/rockchip/Makefile | 4 +-\n drivers/pinctrl/rockchip/pinctrl_rk3128.c | 192 +++++++++\n 4 files changed, 755 insertions(+), 2 deletions(-)\n create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3128.h\n create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3128.c","diff":"diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3128.h b/arch/arm/include/asm/arch-rockchip/grf_rk3128.h\nnew file mode 100644\nindex 0000000..5da6cd2\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3128.h\n@@ -0,0 +1,551 @@\n+/*\n+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd\n+ *\n+ * SPDX-License-Identifier: GPL-2.0+\n+ */\n+#ifndef _ASM_ARCH_GRF_RK3128_H\n+#define _ASM_ARCH_GRF_RK3128_H\n+\n+#include \n+\n+struct rk3128_grf {\n+\tunsigned int reserved[0x2a];\n+\tunsigned int gpio0a_iomux;\n+\tunsigned int gpio0b_iomux;\n+\tunsigned int gpio0c_iomux;\n+\tunsigned int gpio0d_iomux;\n+\tunsigned int gpio1a_iomux;\n+\tunsigned int gpio1b_iomux;\n+\tunsigned int gpio1c_iomux;\n+\tunsigned int gpio1d_iomux;\n+\tunsigned int gpio2a_iomux;\n+\tunsigned int gpio2b_iomux;\n+\tunsigned int gpio2c_iomux;\n+\tunsigned int gpio2d_iomux;\n+\tunsigned int gpio3a_iomux;\n+\tunsigned int gpio3b_iomux;\n+\tunsigned int gpio3c_iomux;\n+\tunsigned int gpio3d_iomux;\n+\tunsigned int gpio2c_iomux2;\n+\tunsigned int grf_cif_iomux;\n+\tunsigned int grf_cif_iomux1;\n+\tunsigned int reserved1[(0x118 - 0xf0) / 4 - 1];\n+\tunsigned int gpio0l_pull;\n+\tunsigned int gpio0h_pull;\n+\tunsigned int gpio1l_pull;\n+\tunsigned int gpio1h_pull;\n+\tunsigned int gpio2l_pull;\n+\tunsigned int gpio2h_pull;\n+\tunsigned int gpio3l_pull;\n+\tunsigned int gpio3h_pull;\n+\tunsigned int reserved2;\n+\tunsigned int soc_con0;\n+\tunsigned int soc_con1;\n+\tunsigned int soc_con2;\n+\tunsigned int soc_status0;\n+\tunsigned int reserved3[6];\n+\tunsigned int mac_con0;\n+\tunsigned int mac_con1;\n+\tunsigned int reserved4[4];\n+\tunsigned int uoc0_con0;\n+\tunsigned int reserved5;\n+\tunsigned int uoc1_con1;\n+\tunsigned int uoc1_con2;\n+\tunsigned int uoc1_con3;\n+\tunsigned int uoc1_con4;\n+\tunsigned int uoc1_con5;\n+\tunsigned int reserved6;\n+\tunsigned int ddrc_stat;\n+\tunsigned int reserved9;\n+\tunsigned int soc_status1;\n+\tunsigned int cpu_con0;\n+\tunsigned int cpu_con1;\n+\tunsigned int cpu_con2;\n+\tunsigned int cpu_con3;\n+\tunsigned int reserved10;\n+\tunsigned int reserved11;\n+\tunsigned int cpu_status0;\n+\tunsigned int cpu_status1;\n+\tunsigned int os_reg[8];\n+\tunsigned int reserved12[(0x280 - 0x1e4) / 4 - 1];\n+\tunsigned int usbphy0_con[8];\n+\tunsigned int usbphy1_con[8];\n+\tunsigned int uoc_status0;\n+\tunsigned int reserved13[(0x300 - 0x2c0) / 4 - 1];\n+\tunsigned int chip_tag;\n+\tunsigned int sdmmc_det_cnt;\n+};\n+check_member(rk3128_grf, sdmmc_det_cnt, 0x304);\n+\n+struct rk3128_pmu {\n+\tunsigned int wakeup_cfg;\n+\tunsigned int pwrdn_con;\n+\tunsigned int pwrdn_st;\n+\tunsigned int idle_req;\n+\tunsigned int idle_st;\n+\tunsigned int pwrmode_con;\n+\tunsigned int pwr_state;\n+\tunsigned int osc_cnt;\n+\tunsigned int core_pwrdwn_cnt;\n+\tunsigned int core_pwrup_cnt;\n+\tunsigned int sft_con;\n+\tunsigned int ddr_sref_st;\n+\tunsigned int int_con;\n+\tunsigned int int_st;\n+\tunsigned int sys_reg[4];\n+};\n+check_member(rk3128_pmu, int_st, 0x34);\n+\n+/* GRF_GPIO0A_IOMUX */\n+enum {\n+\tGPIO0A7_SHIFT\t\t= 14,\n+\tGPIO0A7_MASK\t\t= 3 << GPIO0A7_SHIFT,\n+\tGPIO0A7_GPIO\t\t= 0,\n+\tGPIO0A7_I2C3_SDA,\n+\n+\tGPIO0A6_SHIFT\t\t= 12,\n+\tGPIO0A6_MASK\t\t= 3 << GPIO0A6_SHIFT,\n+\tGPIO0A6_GPIO\t\t= 0,\n+\tGPIO0A6_I2C3_SCL,\n+\n+\tGPIO0A3_SHIFT\t\t= 6,\n+\tGPIO0A3_MASK\t\t= 3 << GPIO0A3_SHIFT,\n+\tGPIO0A3_GPIO\t\t= 0,\n+\tGPIO0A3_I2C1_SDA,\n+\n+\tGPIO0A2_SHIFT\t\t= 4,\n+\tGPIO0A2_MASK\t\t= 1 << GPIO0A2_SHIFT,\n+\tGPIO0A2_GPIO\t\t= 0,\n+\tGPIO0A2_I2C1_SCL,\n+\n+\tGPIO0A1_SHIFT\t\t= 2,\n+\tGPIO0A1_MASK\t\t= 1 << GPIO0A1_SHIFT,\n+\tGPIO0A1_GPIO\t\t= 0,\n+\tGPIO0A1_I2C0_SDA,\n+\n+\tGPIO0A0_SHIFT\t\t= 0,\n+\tGPIO0A0_MASK\t\t= 1 << GPIO0A0_SHIFT,\n+\tGPIO0A0_GPIO\t\t= 0,\n+\tGPIO0A0_I2C0_SCL,\n+};\n+\n+/* GRF_GPIO0B_IOMUX */\n+enum {\n+\tGPIO0B6_SHIFT\t\t= 12,\n+\tGPIO0B6_MASK\t\t= 3 << GPIO0B6_SHIFT,\n+\tGPIO0B6_GPIO\t\t= 0,\n+\tGPIO0B6_I2S_SDI,\n+\tGPIO0B6_SPI_CSN0,\n+\n+\tGPIO0B5_SHIFT\t\t= 10,\n+\tGPIO0B5_MASK\t\t= 3 << GPIO0B5_SHIFT,\n+\tGPIO0B5_GPIO\t\t= 0,\n+\tGPIO0B5_I2S_SDO,\n+\tGPIO0B5_SPI_RXD,\n+\n+\tGPIO0B4_SHIFT\t\t= 8,\n+\tGPIO0B4_MASK\t\t= 1 << GPIO0B4_SHIFT,\n+\tGPIO0B4_GPIO\t\t= 0,\n+\tGPIO0B4_I2S_LRCKTX,\n+\n+\tGPIO0B3_SHIFT\t\t= 6,\n+\tGPIO0B3_MASK\t\t= 3 << GPIO0B3_SHIFT,\n+\tGPIO0B3_GPIO\t\t= 0,\n+\tGPIO0B3_I2S_LRCKRX,\n+\tGPIO0B3_SPI_TXD,\n+\n+\tGPIO0B1_SHIFT\t\t= 2,\n+\tGPIO0B1_MASK\t\t= 3,\n+\tGPIO0B1_GPIO\t\t= 0,\n+\tGPIO0B1_I2S_SCLK,\n+\tGPIO0B1_SPI_CLK,\n+\n+\tGPIO0B0_SHIFT\t\t= 0,\n+\tGPIO0B0_MASK\t\t= 3,\n+\tGPIO0B0_GPIO\t\t= 0,\n+\tGPIO0B0_I2S1_MCLK,\n+};\n+\n+/* GRF_GPIO0D_IOMUX */\n+enum {\n+\tGPIO0D4_SHIFT\t\t= 8,\n+\tGPIO0D4_MASK\t\t= 1 << GPIO0D4_SHIFT,\n+\tGPIO0D4_GPIO\t\t= 0,\n+\tGPIO0D4_PWM2,\n+\n+\tGPIO0D3_SHIFT\t\t= 6,\n+\tGPIO0D3_MASK\t\t= 1 << GPIO0D3_SHIFT,\n+\tGPIO0D3_GPIO\t\t= 0,\n+\tGPIO0D3_PWM1,\n+\n+\tGPIO0D2_SHIFT\t\t= 4,\n+\tGPIO0D2_MASK\t\t= 1 << GPIO0D2_SHIFT,\n+\tGPIO0D2_GPIO\t\t= 0,\n+\tGPIO0D2_PWM0,\n+\n+\tGPIO0D1_SHIFT\t\t= 2,\n+\tGPIO0D1_MASK\t\t= 1 << GPIO0D1_SHIFT,\n+\tGPIO0D1_GPIO\t\t= 0,\n+\tGPIO0D1_UART2_CTSN,\n+\n+\tGPIO0D0_SHIFT\t\t= 0,\n+\tGPIO0D0_MASK\t\t= 3 << GPIO0D0_SHIFT,\n+\tGPIO0D0_GPIO\t\t= 0,\n+\tGPIO0D0_UART2_RTSN,\n+\tGPIO0D0_PMIC_SLEEP,\n+};\n+\n+/* GRF_GPIO1A_IOMUX */\n+enum {\n+\tGPIO1A5_SHIFT\t\t= 10,\n+\tGPIO1A5_MASK\t\t= 3 << GPIO1A5_SHIFT,\n+\tGPIO1A5_GPIO\t\t= 0,\n+\tGPIO1A5_I2S_SDI,\n+\tGPIO1A5_SDMMC_DATA3,\n+\n+\tGPIO1A4_SHIFT\t\t= 8,\n+\tGPIO1A4_MASK\t\t= 3 << GPIO1A4_SHIFT,\n+\tGPIO1A4_GPIO\t\t= 0,\n+\tGPIO1A4_I2S_SD0,\n+\tGPIO1A4_SDMMC_DATA2,\n+\n+\tGPIO1A3_SHIFT\t\t= 6,\n+\tGPIO1A3_MASK\t\t= 1 << GPIO1A3_SHIFT,\n+\tGPIO1A3_GPIO\t\t= 0,\n+\tGPIO1A3_I2S_LRCKTX,\n+\n+\tGPIO1A2_SHIFT\t\t= 4,\n+\tGPIO1A2_MASK\t\t= 3 << GPIO1A2_SHIFT,\n+\tGPIO1A2_GPIO\t\t= 0,\n+\tGPIO1A2_I2S_LRCKRX,\n+\tGPIO1A2_SDMMC_DATA1,\n+\n+\tGPIO1A1_SHIFT\t\t= 2,\n+\tGPIO1A1_MASK\t\t= 3 << GPIO1A1_SHIFT,\n+\tGPIO1A1_GPIO\t\t= 0,\n+\tGPIO1A1_I2S_SCLK,\n+\tGPIO1A1_SDMMC_DATA0,\n+\tGPIO1A1_PMIC_SLEEP,\n+\n+\tGPIO1A0_SHIFT\t\t= 0,\n+\tGPIO1A0_MASK\t\t= 3,\n+\tGPIO1A0_GPIO\t\t= 0,\n+\tGPIO1A0_I2S_MCLK,\n+\tGPIO1A0_SDMMC_CLKOUT,\n+\tGPIO1A0_XIN32K,\n+\n+};\n+\n+/* GRF_GPIO1B_IOMUX */\n+enum {\n+\tGPIO1B7_SHIFT\t\t= 14,\n+\tGPIO1B7_MASK\t\t= 1 << GPIO1B7_SHIFT,\n+\tGPIO1B7_GPIO\t\t= 0,\n+\tGPIO1B7_MMC0_CMD,\n+\n+\tGPIO1B6_SHIFT\t\t= 12,\n+\tGPIO1B6_MASK\t\t= 1 << GPIO1B6_SHIFT,\n+\tGPIO1B6_GPIO\t\t= 0,\n+\tGPIO1B6_MMC_PWREN,\n+\n+\tGPIO1B2_SHIFT\t\t= 4,\n+\tGPIO1B2_MASK\t\t= 3 << GPIO1B2_SHIFT,\n+\tGPIO1B2_GPIO\t\t= 0,\n+\tGPIO1B2_SPI_RXD,\n+\tGPIO1B2_UART1_SIN,\n+\n+\tGPIO1B1_SHIFT\t\t= 2,\n+\tGPIO1B1_MASK\t\t= 3 << GPIO1B1_SHIFT,\n+\tGPIO1B1_GPIO\t\t= 0,\n+\tGPIO1B1_SPI_TXD,\n+\tGPIO1B1_UART1_SOUT,\n+\n+\tGPIO1B0_SHIFT\t\t= 0,\n+\tGPIO1B0_MASK\t\t= 3 << GPIO1B0_SHIFT,\n+\tGPIO1B0_GPIO\t\t= 0,\n+\tGPIO1B0_SPI_CLK,\n+\tGPIO1B0_UART1_CTSN\n+};\n+\n+/* GRF_GPIO1C_IOMUX */\n+enum {\n+\tGPIO1C6_SHIFT\t\t= 12,\n+\tGPIO1C6_MASK\t\t= 3 << GPIO1C6_SHIFT,\n+\tGPIO1C6_GPIO\t\t= 0,\n+\tGPIO1C6_NAND_CS2,\n+\tGPIO1C6_EMMC_CMD,\n+\n+\tGPIO1C5_SHIFT\t\t= 10,\n+\tGPIO1C5_MASK\t\t= 3 << GPIO1C5_SHIFT,\n+\tGPIO1C5_GPIO\t\t= 0,\n+\tGPIO1C5_MMC0_D3,\n+\tGPIO1C5_JTAG_TMS,\n+\n+\tGPIO1C4_SHIFT\t\t= 8,\n+\tGPIO1C4_MASK\t\t= 3 << GPIO1C4_SHIFT,\n+\tGPIO1C4_GPIO\t\t= 0,\n+\tGPIO1C4_MMC0_D2,\n+\tGPIO1C4_JTAG_TCK,\n+\n+\tGPIO1C3_SHIFT\t\t= 6,\n+\tGPIO1C3_MASK\t\t= 3 << GPIO1C3_SHIFT,\n+\tGPIO1C3_GPIO\t\t= 0,\n+\tGPIO1C3_MMC0_D1,\n+\tGPIO1C3_UART2_RX,\n+\n+\tGPIO1C2_SHIFT\t\t= 4,\n+\tGPIO1C2_MASK\t\t= 3 << GPIO1C2_SHIFT ,\n+\tGPIO1C2_GPIO\t\t= 0,\n+\tGPIO1C2_MMC0_D0,\n+\tGPIO1C2_UART2_TX,\n+\n+\tGPIO1C1_SHIFT\t\t= 2,\n+\tGPIO1C1_MASK\t\t= 1 << GPIO1C1_SHIFT,\n+\tGPIO1C1_GPIO\t\t= 0,\n+\tGPIO1C1_MMC0_DETN,\n+\n+\tGPIO1C0_SHIFT\t\t= 0,\n+\tGPIO1C0_MASK\t\t= 1 << GPIO1C0_SHIFT,\n+\tGPIO1C0_GPIO\t\t= 0,\n+\tGPIO1C0_MMC0_CLKOUT,\n+};\n+\n+/* GRF_GPIO1D_IOMUX */\n+enum {\n+\tGPIO1D7_SHIFT\t\t= 14,\n+\tGPIO1D7_MASK\t\t= 3 << GPIO1D7_SHIFT,\n+\tGPIO1D7_GPIO\t\t= 0,\n+\tGPIO1D7_NAND_D7,\n+\tGPIO1D7_EMMC_D7,\n+\tGPIO1D7_SPI_CSN1,\n+\n+\tGPIO1D6_SHIFT\t\t= 12,\n+\tGPIO1D6_MASK\t\t= 3 << GPIO1D6_SHIFT,\n+\tGPIO1D6_GPIO\t\t= 0,\n+\tGPIO1D6_NAND_D6,\n+\tGPIO1D6_EMMC_D6,\n+\tGPIO1D6_SPI_CSN0,\n+\n+\tGPIO1D5_SHIFT\t\t= 10,\n+\tGPIO1D5_MASK\t\t= 3 << GPIO1D5_SHIFT,\n+\tGPIO1D5_GPIO\t\t= 0,\n+\tGPIO1D5_NAND_D5,\n+\tGPIO1D5_EMMC_D5,\n+\tGPIO1D5_SPI_TXD1,\n+\n+\tGPIO1D4_SHIFT\t\t= 8,\n+\tGPIO1D4_MASK\t\t= 3 << GPIO1D4_SHIFT,\n+\tGPIO1D4_GPIO\t\t= 0,\n+\tGPIO1D4_NAND_D4,\n+\tGPIO1D4_EMMC_D4,\n+\tGPIO1D4_SPI_RXD1,\n+\n+\tGPIO1D3_SHIFT\t\t= 6,\n+\tGPIO1D3_MASK\t\t= 3 << GPIO1D3_SHIFT,\n+\tGPIO1D3_GPIO\t\t= 0,\n+\tGPIO1D3_NAND_D3,\n+\tGPIO1D3_EMMC_D3,\n+\tGPIO1D3_SFC_SIO3,\n+\n+\tGPIO1D2_SHIFT\t\t= 4,\n+\tGPIO1D2_MASK\t\t= 3 << GPIO1D2_SHIFT,\n+\tGPIO1D2_GPIO\t\t= 0,\n+\tGPIO1D2_NAND_D2,\n+\tGPIO1D2_EMMC_D2,\n+\tGPIO1D2_SFC_SIO2,\n+\n+\tGPIO1D1_SHIFT\t\t= 2,\n+\tGPIO1D1_MASK\t\t= 3 << GPIO1D1_SHIFT,\n+\tGPIO1D1_GPIO\t\t= 0,\n+\tGPIO1D1_NAND_D1,\n+\tGPIO1D1_EMMC_D1,\n+\tGPIO1D1_SFC_SIO1,\n+\n+\tGPIO1D0_SHIFT\t\t= 0,\n+\tGPIO1D0_MASK\t\t= 3 << GPIO1D0_SHIFT,\n+\tGPIO1D0_GPIO\t\t= 0,\n+\tGPIO1D0_NAND_D0,\n+\tGPIO1D0_EMMC_D0,\n+\tGPIO1D0_SFC_SIO0,\n+};\n+\n+/* GRF_GPIO2A_IOMUX */\n+enum {\n+\tGPIO2A7_SHIFT\t\t= 14,\n+\tGPIO2A7_MASK\t\t= 3 << GPIO2A7_SHIFT,\n+\tGPIO2A7_GPIO\t\t= 0,\n+\tGPIO2A7_NAND_DQS,\n+\tGPIO2A7_EMMC_CLKOUT,\n+\n+\tGPIO2A6_SHIFT\t\t= 12,\n+\tGPIO2A6_MASK\t\t= 1 << GPIO2A6_SHIFT,\n+\tGPIO2A6_GPIO\t\t= 0,\n+\tGPIO2A6_NAND_CS0,\n+\n+\tGPIO2A5_SHIFT\t\t= 10,\n+\tGPIO2A5_MASK\t\t= 3 << GPIO2A5_SHIFT,\n+\tGPIO2A5_GPIO\t\t= 0,\n+\tGPIO2A5_NAND_WP,\n+\tGPIO2A5_EMMC_PWREN,\n+\n+\tGPIO2A4_SHIFT\t\t= 8,\n+\tGPIO2A4_MASK\t\t= 3 << GPIO2A4_SHIFT,\n+\tGPIO2A4_GPIO\t\t= 0,\n+\tGPIO2A4_NAND_RDY,\n+\tGPIO2A4_EMMC_CMD,\n+\tGPIO2A3_SFC_CLK,\n+\n+\tGPIO2A3_SHIFT\t\t= 6,\n+\tGPIO2A3_MASK\t\t= 3 << GPIO2A3_SHIFT,\n+\tGPIO2A3_GPIO\t\t= 0,\n+\tGPIO2A3_NAND_RDN,\n+\tGPIO2A4_SFC_CSN1,\n+\n+\tGPIO2A2_SHIFT\t\t= 4,\n+\tGPIO2A2_MASK\t\t= 3 << GPIO2A2_SHIFT,\n+\tGPIO2A2_GPIO\t\t= 0,\n+\tGPIO2A2_NAND_WRN,\n+\tGPIO2A4_SFC_CSN0,\n+\n+\tGPIO2A1_SHIFT\t\t= 2,\n+\tGPIO2A1_MASK\t\t= 3 << GPIO2A1_SHIFT,\n+\tGPIO2A1_GPIO\t\t= 0,\n+\tGPIO2A1_NAND_CLE,\n+\tGPIO2A1_EMMC_CLKOUT,\n+\n+\tGPIO2A0_SHIFT\t\t= 0,\n+\tGPIO2A0_MASK\t\t= 3 << GPIO2A0_SHIFT,\n+\tGPIO2A0_GPIO\t\t= 0,\n+\tGPIO2A0_NAND_ALE,\n+\tGPIO2A0_SPI_CLK,\n+};\n+\n+/* GRF_GPIO2B_IOMUX */\n+enum {\n+\tGPIO2B7_SHIFT\t\t= 14,\n+\tGPIO2B7_MASK\t\t= 3 << GPIO2B7_SHIFT,\n+\tGPIO2B7_GPIO\t\t= 0,\n+\tGPIO2B7_LCDC0_D13,\n+\tGPIO2B7_EBC_SDCE5,\n+\tGPIO2B7_GMAC_RXER,\n+\n+\tGPIO2B6_SHIFT\t\t= 12,\n+\tGPIO2B6_MASK\t\t= 3 << GPIO2B6_SHIFT,\n+\tGPIO2B6_GPIO\t\t= 0,\n+\tGPIO2B6_LCDC0_D12,\n+\tGPIO2B6_EBC_SDCE4,\n+\tGPIO2B6_GMAC_CLK,\n+\n+\tGPIO2B5_SHIFT\t\t= 10,\n+\tGPIO2B5_MASK\t\t= 3 << GPIO2B5_SHIFT,\n+\tGPIO2B5_GPIO\t\t= 0,\n+\tGPIO2B5_LCDC0_D11,\n+\tGPIO2B5_EBC_SDCE3,\n+\tGPIO2B5_GMAC_TXEN,\n+\n+\tGPIO2B4_SHIFT\t\t= 8,\n+\tGPIO2B4_MASK\t\t= 3 << GPIO2B4_SHIFT,\n+\tGPIO2B4_GPIO\t\t= 0,\n+\tGPIO2B4_LCDC0_D10,\n+\tGPIO2B4_EBC_SDCE2,\n+\tGPIO2B4_GMAC_MDIO,\n+\n+\tGPIO2B3_SHIFT\t\t= 6,\n+\tGPIO2B3_MASK\t\t= 3 << GPIO2B3_SHIFT,\n+\tGPIO2B3_GPIO\t\t= 0,\n+\tGPIO2B3_LCDC0_DEN,\n+\tGPIO2B3_EBC_GDCLK,\n+\tGPIO2B3_GMAC_RXCLK,\n+\n+\tGPIO2B2_SHIFT\t\t= 4,\n+\tGPIO2B2_MASK\t\t= 3 << GPIO2B2_SHIFT,\n+\tGPIO2B2_GPIO\t\t= 0,\n+\tGPIO2B2_LCDC0_VSYNC,\n+\tGPIO2B2_EBC_SDOE,\n+\tGPIO2B2_GMAC_CRS,\n+\n+\tGPIO2B1_SHIFT\t\t= 2,\n+\tGPIO2B1_MASK\t\t= 3 << GPIO2B1_SHIFT,\n+\tGPIO2B1_GPIO\t\t= 0,\n+\tGPIO2B1_LCDC0_HSYNC,\n+\tGPIO2B1_EBC_SDLE,\n+\tGPIO2B1_GMAC_TXCLK,\n+\n+\tGPIO2B0_SHIFT\t\t= 0,\n+\tGPIO2B0_MASK\t\t= 3 << GPIO2B0_SHIFT,\n+\tGPIO2B0_GPIO\t\t= 0,\n+\tGPIO2B0_LCDC0_DCLK,\n+\tGPIO2B0_EBC_SDCLK,\n+\tGPIO2B0_GMAC_RXDV,\n+};\n+\n+/* GRF_GPIO2C_IOMUX */\n+enum {\n+\tGPIO2C3_SHIFT\t\t= 6,\n+\tGPIO2C3_MASK\t\t= 3 << GPIO2C3_SHIFT,\n+\tGPIO2C3_GPIO\t\t= 0,\n+\tGPIO2C3_LCDC0_D17,\n+\tGPIO2C3_EBC_GDPWR0,\n+\tGPIO2C3_GMAC_TXD0,\n+\n+\tGPIO2C2_SHIFT\t\t= 4,\n+\tGPIO2C2_MASK\t\t= 3 << GPIO2C2_SHIFT,\n+\tGPIO2C2_GPIO\t\t= 0,\n+\tGPIO2C2_LCDC0_D16,\n+\tGPIO2C2_EBC_GDSP,\n+\tGPIO2C2_GMAC_TXD1,\n+\n+\tGPIO2C1_SHIFT\t\t= 2,\n+\tGPIO2C1_MASK\t\t= 3 << GPIO2C1_SHIFT,\n+\tGPIO2C1_GPIO\t\t= 0,\n+\tGPIO2C1_LCDC0_D15,\n+\tGPIO2C1_EBC_GDOE,\n+\tGPIO2C1_GMAC_RXD0,\n+\n+\tGPIO2C0_SHIFT\t\t= 0,\n+\tGPIO2C0_MASK\t\t= 3 << GPIO2C0_SHIFT,\n+\tGPIO2C0_GPIO\t\t= 0,\n+\tGPIO2C0_LCDC0_D14,\n+\tGPIO2C0_EBC_VCOM,\n+\tGPIO2C0_GMAC_RXD1,\n+};\n+\n+/* GRF_GPIO2D_IOMUX */\n+enum {\n+\tGPIO2D6_SHIFT\t\t= 12,\n+\tGPIO2D6_MASK\t\t= 3 << GPIO2D6_SHIFT,\n+\tGPIO2D6_GPIO\t\t= 0,\n+\tGPIO2D6_LCDC0_D22,\n+\tGPIO2D6_GMAC_COL\t= 4,\n+\n+\tGPIO2D1_SHIFT\t\t= 2,\n+\tGPIO2D1_MASK\t\t= 3 << GPIO2D1_SHIFT,\n+\tGPIO2D1_GPIO\t\t= 0,\n+\tGPIO2D1_GMAC_MDC\t= 3,\n+};\n+\n+/* GRF_GPIO2C_IOMUX2 */\n+enum {\n+\tGPIO2C7_SHIFT\t\t= 12,\n+\tGPIO2C7_MASK\t\t= 7 << GPIO2C7_SHIFT,\n+\tGPIO2C7_GPIO\t\t= 0,\n+\tGPIO2C7_GMAC_TXD3\t= 4,\n+\n+\tGPIO2C6_SHIFT\t\t= 12,\n+\tGPIO2C6_MASK\t\t= 7 << GPIO2C6_SHIFT,\n+\tGPIO2C6_GPIO\t\t= 0,\n+\tGPIO2C6_GMAC_TXD2\t= 4,\n+\n+\tGPIO2C5_SHIFT\t\t= 12,\n+\tGPIO2C5_MASK\t\t= 7 << GPIO2C5_SHIFT,\n+\tGPIO2C5_GPIO\t\t= 0,\n+\tGPIO2C5_I2C2_SCL\t= 3,\n+\tGPIO2C5_GMAC_RXD2,\n+\n+\tGPIO2C4_SHIFT\t\t= 12,\n+\tGPIO2C4_MASK\t\t= 7 << GPIO2C4_SHIFT,\n+\tGPIO2C4_GPIO\t\t= 0,\n+\tGPIO2C4_I2C2_SDA\t= 3,\n+\tGPIO2C4_GMAC_RXD2,\n+};\n+#endif\ndiff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig\nindex bcbe4a1..35a7c62 100644\n--- a/drivers/pinctrl/Kconfig\n+++ b/drivers/pinctrl/Kconfig\n@@ -168,6 +168,16 @@ config PINCTRL_ROCKCHIP_RK3036\n \t the GPIO definitions and pin control functions for each available\n \t multiplex function.\n \n+config PINCTRL_ROCKCHIP_RK3128\n+\tbool \"Rockchip rk3128 pin control driver\"\n+\tdepends on DM\n+\thelp\n+\t Support pin multiplexing control on Rockchip rk3128 SoCs.\n+\n+\t The driver is controlled by a device tree node which contains both\n+\t the GPIO definitions and pin control functions for each available\n+\t multiplex function.\n+\n config PINCTRL_ROCKCHIP_RK3188\n \tbool \"Rockchip rk3188 pin control driver\"\n \tdepends on DM\ndiff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile\nindex 5251771..f09c6e1 100644\n--- a/drivers/pinctrl/rockchip/Makefile\n+++ b/drivers/pinctrl/rockchip/Makefile\n@@ -1,11 +1,11 @@\n #\n-# Copyright (c) 2015 Google, Inc\n-# Written by Simon Glass \n+# Copyright (c) 2017 Rockchip Electronics Co., Ltd\n #\n # SPDX-License-Identifier:\tGPL-2.0+\n #\n \n obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o\n+obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3128) += pinctrl_rk3128.o\n obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o\n obj-$(CONFIG_PINCTRL_ROCKCHIP_RK322X) += pinctrl_rk322x.o\n obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o\ndiff --git a/drivers/pinctrl/rockchip/pinctrl_rk3128.c b/drivers/pinctrl/rockchip/pinctrl_rk3128.c\nnew file mode 100644\nindex 0000000..3d1656b\n--- /dev/null\n+++ b/drivers/pinctrl/rockchip/pinctrl_rk3128.c\n@@ -0,0 +1,192 @@\n+/*\n+ * Pinctrl driver for Rockchip 3128 SoCs\n+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd\n+ *\n+ * SPDX-License-Identifier: GPL-2.0+\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+struct rk3128_pinctrl_priv {\n+\tstruct rk3128_grf *grf;\n+};\n+\n+static void pinctrl_rk3128_i2c_config(struct rk3128_grf *grf, int i2c_id)\n+{\n+\tswitch (i2c_id) {\n+\tcase PERIPH_ID_I2C0:\n+\t\trk_clrsetreg(&grf->gpio0a_iomux,\n+\t\t\t GPIO0A1_MASK | GPIO0A0_MASK,\n+\t\t\t GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |\n+\t\t\t GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);\n+\n+\t\tbreak;\n+\tcase PERIPH_ID_I2C1:\n+\t\trk_clrsetreg(&grf->gpio0a_iomux,\n+\t\t\t GPIO0A3_MASK | GPIO0A2_MASK,\n+\t\t\t GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |\n+\t\t\t GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);\n+\t\tbreak;\n+\tcase PERIPH_ID_I2C2:\n+\t\trk_clrsetreg(&grf->gpio2c_iomux2,\n+\t\t\t GPIO2C5_MASK | GPIO2C4_MASK,\n+\t\t\t GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |\n+\t\t\t GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);\n+\t\tbreak;\n+\tcase PERIPH_ID_I2C3:\n+\t\trk_clrsetreg(&grf->gpio0a_iomux,\n+\t\t\t GPIO0A7_MASK | GPIO0A6_MASK,\n+\t\t\t GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |\n+\t\t\t GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);\n+\n+\t\tbreak;\n+\t}\n+}\n+\n+static void pinctrl_rk3128_sdmmc_config(struct rk3128_grf *grf, int mmc_id)\n+{\n+\tswitch (mmc_id) {\n+\tcase PERIPH_ID_EMMC:\n+\t\tprintf(\"%s 0\\n\", __func__);\n+\t\trk_clrsetreg(&grf->gpio1d_iomux, 0xffff,\n+\t\t\t GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |\n+\t\t\t GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |\n+\t\t\t GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |\n+\t\t\t GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |\n+\t\t\t GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |\n+\t\t\t GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |\n+\t\t\t GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |\n+\t\t\t GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);\n+\t\trk_clrsetreg(&grf->gpio2a_iomux,\n+\t\t\t GPIO2A4_MASK | GPIO2A5_MASK | GPIO2A7_MASK,\n+\t\t\t GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT |\n+\t\t\t GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |\n+\t\t\t GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);\n+\t\tprintf(\"%s 1\\n\", __func__);\n+\t\tbreak;\n+\tcase PERIPH_ID_SDCARD:\n+\t\tprintf(\"%s 2 %p\\n\", __func__, &grf->gpio1c_iomux);\n+\t\trk_clrsetreg(&grf->gpio1c_iomux, 0x0fff,\n+\t\t\t GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT |\n+\t\t\t GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT |\n+\t\t\t GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT |\n+\t\t\t GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT |\n+\t\t\t GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT |\n+\t\t\t GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT);\n+\t\tprintf(\"%s 3\\n\", __func__);\n+\t\tbreak;\n+\t}\n+}\n+\n+static int rk3128_pinctrl_request(struct udevice *dev, int func, int flags)\n+{\n+\tstruct rk3128_pinctrl_priv *priv = dev_get_priv(dev);\n+\n+\tdebug(\"%s: func=%x, flags=%x\\n\", __func__, func, flags);\n+\tswitch (func) {\n+\tcase PERIPH_ID_I2C0:\n+\tcase PERIPH_ID_I2C1:\n+\tcase PERIPH_ID_I2C2:\n+\tcase PERIPH_ID_I2C3:\n+\t\tpinctrl_rk3128_i2c_config(priv->grf, func);\n+\t\tbreak;\n+\tcase PERIPH_ID_SDMMC0:\n+\tcase PERIPH_ID_SDMMC1:\n+\t\tpinctrl_rk3128_sdmmc_config(priv->grf, func);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int rk3128_pinctrl_get_periph_id(struct udevice *dev,\n+\t\t\t\t\tstruct udevice *periph)\n+{\n+\tu32 cell[3];\n+\tint ret;\n+\n+\tret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),\n+\t\t\t\t \"interrupts\", cell, ARRAY_SIZE(cell));\n+\tif (ret < 0)\n+\t\treturn -EINVAL;\n+\n+\tswitch (cell[1]) {\n+\tcase 14:\n+\t\treturn PERIPH_ID_SDCARD;\n+\tcase 16:\n+\t\treturn PERIPH_ID_EMMC;\n+\tcase 20:\n+\t\treturn PERIPH_ID_UART0;\n+\tcase 21:\n+\t\treturn PERIPH_ID_UART1;\n+\tcase 22:\n+\t\treturn PERIPH_ID_UART2;\n+\tcase 23:\n+\t\treturn PERIPH_ID_SPI0;\n+\tcase 24:\n+\t\treturn PERIPH_ID_I2C0;\n+\tcase 25:\n+\t\treturn PERIPH_ID_I2C1;\n+\tcase 26:\n+\t\treturn PERIPH_ID_I2C2;\n+\tcase 27:\n+\t\treturn PERIPH_ID_I2C3;\n+\tcase 30:\n+\t\treturn PERIPH_ID_PWM0;\n+\t}\n+\treturn -ENOENT;\n+}\n+\n+static int rk3128_pinctrl_set_state_simple(struct udevice *dev,\n+\t\t\t\t\t struct udevice *periph)\n+{\n+\tint func;\n+\n+\tfunc = rk3128_pinctrl_get_periph_id(dev, periph);\n+\tif (func < 0)\n+\t\treturn func;\n+\treturn rk3128_pinctrl_request(dev, func, 0);\n+}\n+\n+static struct pinctrl_ops rk3128_pinctrl_ops = {\n+\t.set_state_simple\t= rk3128_pinctrl_set_state_simple,\n+\t.request\t= rk3128_pinctrl_request,\n+\t.get_periph_id\t= rk3128_pinctrl_get_periph_id,\n+};\n+\n+static int rk3128_pinctrl_probe(struct udevice *dev)\n+{\n+\tstruct rk3128_pinctrl_priv *priv = dev_get_priv(dev);\n+\n+\tpriv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n+\tdebug(\"%s: grf=%p\\n\", __func__, priv->grf);\n+\treturn 0;\n+}\n+\n+static const struct udevice_id rk3128_pinctrl_ids[] = {\n+\t{ .compatible = \"rockchip,rk3128-pinctrl\" },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(pinctrl_rk3128) = {\n+\t.name\t\t= \"pinctrl_rk3128\",\n+\t.id\t\t= UCLASS_PINCTRL,\n+\t.of_match\t= rk3128_pinctrl_ids,\n+\t.priv_auto_alloc_size = sizeof(struct rk3128_pinctrl_priv),\n+\t.ops\t\t= &rk3128_pinctrl_ops,\n+\t.bind\t\t= dm_scan_fdt_dev,\n+\t.probe\t\t= rk3128_pinctrl_probe,\n+};\n","prefixes":["U-Boot","4/8"]}