{"id":819128,"url":"http://patchwork.ozlabs.org/api/patches/819128/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506515969-1472-3-git-send-email-kever.yang@rock-chips.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506515969-1472-3-git-send-email-kever.yang@rock-chips.com>","list_archive_url":null,"date":"2017-09-27T12:39:23","name":"[U-Boot,2/8] rockchip: rk3128: add soc basic support","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"d4a66dfbba43e87bcc9dd90d63974990b0e5e76f","submitter":{"id":64532,"url":"http://patchwork.ozlabs.org/api/people/64532/?format=json","name":"Kever Yang","email":"kever.yang@rock-chips.com"},"delegate":{"id":69486,"url":"http://patchwork.ozlabs.org/api/users/69486/?format=json","username":"ptomsich","first_name":"Philipp","last_name":"Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506515969-1472-3-git-send-email-kever.yang@rock-chips.com/mbox/","series":[{"id":5353,"url":"http://patchwork.ozlabs.org/api/series/5353/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=5353","date":"2017-09-27T12:39:21","name":"rockchip: add new SoC support for RK3128","version":1,"mbox":"http://patchwork.ozlabs.org/series/5353/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/819128/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/819128/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"RK3128 is a SoC from Rockchip with quad-core Cortex-A7 CPU\nand mali400 GPU. Support Nand flash, eMMC, SD card, USB 2.0 host\nand device, HDMI/LVDS/MIPI display.\n\nSigned-off-by: Kever Yang \n---\n\n arch/arm/mach-rockchip/Kconfig | 10 ++\n arch/arm/mach-rockchip/Makefile | 2 +\n arch/arm/mach-rockchip/rk3128-board.c | 146 ++++++++++++++++++++++++++\n arch/arm/mach-rockchip/rk3128/Kconfig | 0\n arch/arm/mach-rockchip/rk3128/Makefile | 8 ++\n arch/arm/mach-rockchip/rk3128/rk3128.c | 12 +++\n arch/arm/mach-rockchip/rk3128/syscon_rk3128.c | 21 ++++\n include/configs/rk3128_common.h | 70 ++++++++++++\n 8 files changed, 269 insertions(+)\n create mode 100644 arch/arm/mach-rockchip/rk3128-board.c\n create mode 100644 arch/arm/mach-rockchip/rk3128/Kconfig\n create mode 100644 arch/arm/mach-rockchip/rk3128/Makefile\n create mode 100644 arch/arm/mach-rockchip/rk3128/rk3128.c\n create mode 100644 arch/arm/mach-rockchip/rk3128/syscon_rk3128.c\n create mode 100644 include/configs/rk3128_common.h","diff":"diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig\nindex e1bc947..7a4f2a1 100644\n--- a/arch/arm/mach-rockchip/Kconfig\n+++ b/arch/arm/mach-rockchip/Kconfig\n@@ -11,6 +11,15 @@ config ROCKCHIP_RK3036\n \t and video codec support. Peripherals include Gigabit Ethernet,\n \t USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.\n \n+config ROCKCHIP_RK3128\n+\tbool \"Support Rockchip RK3128\"\n+\tselect CPU_V7\n+\thelp\n+\t The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7\n+\t including NEON and GPU, Mali-400 graphics, several DDR3 options\n+\t and video codec support. Peripherals include Gigabit Ethernet,\n+\t USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.\n+\n config ROCKCHIP_RK3188\n \tbool \"Support Rockchip RK3188\"\n \tselect CPU_V7\n@@ -173,6 +182,7 @@ config SPL_MMC_SUPPORT\n \tdefault y if !SPL_ROCKCHIP_BACK_TO_BROM\n \n source \"arch/arm/mach-rockchip/rk3036/Kconfig\"\n+source \"arch/arm/mach-rockchip/rk3128/Kconfig\"\n source \"arch/arm/mach-rockchip/rk3188/Kconfig\"\n source \"arch/arm/mach-rockchip/rk322x/Kconfig\"\n source \"arch/arm/mach-rockchip/rk3288/Kconfig\"\ndiff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile\nindex 5ef0938..3974c5e 100644\n--- a/arch/arm/mach-rockchip/Makefile\n+++ b/arch/arm/mach-rockchip/Makefile\n@@ -24,6 +24,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o\n \n ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)\n obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o\n+obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o\n obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o\n obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o\n obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o\n@@ -36,6 +37,7 @@ obj-y += rk_timer.o\n endif\n \n obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/\n+obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/\n ifndef CONFIG_TPL_BUILD\n obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/\n endif\ndiff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c\nnew file mode 100644\nindex 0000000..70eda6f\n--- /dev/null\n+++ b/arch/arm/mach-rockchip/rk3128-board.c\n@@ -0,0 +1,146 @@\n+/*\n+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0+\n+ */\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+#define PMU_BASE\t0x100a0000\n+\n+static void setup_boot_mode(void)\n+{\n+\tstruct rk3128_pmu *const pmu = (void *)PMU_BASE;\n+\tint boot_mode = readl(&pmu->sys_reg[0]);\n+\n+\tdebug(\"boot mode %x.\\n\", boot_mode);\n+\n+\t/* Clear boot mode */\n+\twritel(BOOT_NORMAL, &pmu->sys_reg[0]);\n+\n+\tswitch (boot_mode) {\n+\tcase BOOT_FASTBOOT:\n+\t\tprintf(\"enter fastboot!\\n\");\n+\t\tenv_set(\"preboot\", \"setenv preboot; fastboot usb0\");\n+\t\tbreak;\n+\tcase BOOT_UMS:\n+\t\tprintf(\"enter UMS!\\n\");\n+\t\tenv_set(\"preboot\", \"setenv preboot; ums mmc 0\");\n+\t\tbreak;\n+\tcase BOOT_LOADER:\n+\t\tprintf(\"enter Rockusb!\\n\");\n+\t\tenv_set(\"preboot\", \"setenv preboot; rockusb 0 mmc 0\");\n+\t\tbreak;\n+\t}\n+}\n+\n+__weak int rk_board_late_init(void)\n+{\n+\treturn 0;\n+}\n+\n+int board_late_init(void)\n+{\n+\tsetup_boot_mode();\n+\n+\treturn rk_board_late_init();\n+}\n+\n+int board_init(void)\n+{\n+\trockchip_timer_init();\n+\n+\treturn 0;\n+}\n+\n+int dram_init_banksize(void)\n+{\n+\tgd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;\n+\tgd->bd->bi_dram[0].size = 0x8400000;\n+\t/* Reserve 0x200000 for OPTEE */\n+\tgd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE\n+\t\t\t\t+ gd->bd->bi_dram[0].size + 0x200000;\n+\tgd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start\n+\t\t\t\t+ gd->ram_size - gd->bd->bi_dram[1].start;\n+\n+\treturn 0;\n+}\n+\n+#ifndef CONFIG_SYS_DCACHE_OFF\n+void enable_caches(void)\n+{\n+\t/* Enable D-cache. I-cache is already enabled in start.S */\n+\tdcache_enable();\n+}\n+#endif\n+\n+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)\n+#include \n+#include \n+\n+static struct dwc2_plat_otg_data rk3128_otg_data = {\n+\t.rx_fifo_sz\t= 512,\n+\t.np_tx_fifo_sz\t= 16,\n+\t.tx_fifo_sz\t= 128,\n+};\n+\n+int board_usb_init(int index, enum usb_init_type init)\n+{\n+\tint node;\n+\tconst char *mode;\n+\tbool matched = false;\n+\tconst void *blob = gd->fdt_blob;\n+\n+\t/* find the usb_otg node */\n+\tnode = fdt_node_offset_by_compatible(blob, -1,\n+\t\t\t\t\t\"rockchip,rk3288-usb\");\n+\n+\twhile (node > 0) {\n+\t\tmode = fdt_getprop(blob, node, \"dr_mode\", NULL);\n+\t\tif (mode && strcmp(mode, \"otg\") == 0) {\n+\t\t\tmatched = true;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tnode = fdt_node_offset_by_compatible(blob, node,\n+\t\t\t\t\t\"rockchip,rk3288-usb\");\n+\t}\n+\tif (!matched) {\n+\t\tdebug(\"Not found usb_otg device\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\trk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, \"reg\");\n+\n+\treturn dwc2_udc_probe(&rk3128_otg_data);\n+}\n+\n+int board_usb_cleanup(int index, enum usb_init_type init)\n+{\n+\treturn 0;\n+}\n+#endif\n+\n+#if defined(CONFIG_USB_FUNCTION_FASTBOOT)\n+int fb_set_reboot_flag(void)\n+{\n+\tstruct rk3128_grf *grf;\n+\n+\tprintf(\"Setting reboot to fastboot flag ...\\n\");\n+\tgrf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n+\t/* Set boot mode to fastboot */\n+\twritel(BOOT_FASTBOOT, &grf->os_reg[0]);\n+\n+\treturn 0;\n+}\n+#endif\ndiff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig\nnew file mode 100644\nindex 0000000..e69de29\ndiff --git a/arch/arm/mach-rockchip/rk3128/Makefile b/arch/arm/mach-rockchip/rk3128/Makefile\nnew file mode 100644\nindex 0000000..0f63d92\n--- /dev/null\n+++ b/arch/arm/mach-rockchip/rk3128/Makefile\n@@ -0,0 +1,8 @@\n+#\n+# (C) Copyright 2017 Rockchip Electronics Co., Ltd\n+#\n+# SPDX-License-Identifier: GPL-2.0+\n+#\n+\n+obj-y += rk3128.o\n+obj-y += syscon_rk3128.o\ndiff --git a/arch/arm/mach-rockchip/rk3128/rk3128.c b/arch/arm/mach-rockchip/rk3128/rk3128.c\nnew file mode 100644\nindex 0000000..9d6e3b1\n--- /dev/null\n+++ b/arch/arm/mach-rockchip/rk3128/rk3128.c\n@@ -0,0 +1,12 @@\n+/*\n+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd\n+ *\n+ * SPDX-License-Identifier: GPL-2.0+\n+ */\n+\n+int arch_cpu_init(void)\n+{\n+\t/* We do some SoC one time setting here. */\n+\n+\treturn 0;\n+}\ndiff --git a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c\nnew file mode 100644\nindex 0000000..0b63639\n--- /dev/null\n+++ b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c\n@@ -0,0 +1,21 @@\n+/*\n+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd\n+ *\n+ * SPDX-License-Identifier: GPL-2.0+\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+\n+static const struct udevice_id rk3128_syscon_ids[] = {\n+\t{ .compatible = \"rockchip,rk3128-grf\", .data = ROCKCHIP_SYSCON_GRF },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(syscon_rk3128) = {\n+\t.name = \"rk3128_syscon\",\n+\t.id = UCLASS_SYSCON,\n+\t.of_match = rk3128_syscon_ids,\n+};\ndiff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h\nnew file mode 100644\nindex 0000000..af90132\n--- /dev/null\n+++ b/include/configs/rk3128_common.h\n@@ -0,0 +1,70 @@\n+/*\n+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd\n+ *\n+ * SPDX-License-Identifier: GPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_RK3128_COMMON_H\n+#define __CONFIG_RK3128_COMMON_H\n+\n+#include \"rockchip-common.h\"\n+\n+#define CONFIG_ENV_SIZE\t\t\t0x2000\n+#define CONFIG_SYS_MAXARGS\t\t16\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_SYS_MALLOC_LEN\t\t(32 << 20)\n+#define CONFIG_SYS_CBSIZE\t\t1024\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+\n+#define CONFIG_SYS_TIMER_RATE\t\t(24 * 1000 * 1000)\n+#define CONFIG_SYS_TIMER_BASE\t\t0x200440a0 /* TIMER5 */\n+#define CONFIG_SYS_TIMER_COUNTER\t(CONFIG_SYS_TIMER_BASE + 8)\n+\n+#define CONFIG_SYS_NS16550_MEM32\n+\n+#define CONFIG_SYS_TEXT_BASE\t\t0x60000000\n+#define CONFIG_SYS_INIT_SP_ADDR\t\t0x60100000\n+#define CONFIG_SYS_LOAD_ADDR\t\t0x60800800\n+\n+\n+#define CONFIG_SYS_BOOTM_LEN\t(64 << 20)\t/* 64M */\n+\n+/* MMC/SD IP block */\n+#define CONFIG_BOUNCE_BUFFER\n+\n+#define CONFIG_SUPPORT_VFAT\n+#define CONFIG_FS_EXT4\n+\n+/* RAW SD card / eMMC locations. */\n+#define CONFIG_SYS_SPI_U_BOOT_OFFS\t(128 << 10)\n+\n+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION\t1\n+#define CONFIG_SYS_SDRAM_BASE\t\t0x60000000\n+#define CONFIG_NR_DRAM_BANKS\t\t2\n+#define SDRAM_MAX_SIZE\t\t\t0x80000000\n+\n+#define CONFIG_SPI_FLASH\n+#define CONFIG_SPI\n+#define CONFIG_SF_DEFAULT_SPEED 20000000\n+\n+#ifndef CONFIG_SPL_BUILD\n+\n+/* usb mass storage */\n+#define CONFIG_USB_FUNCTION_MASS_STORAGE\n+\n+#define ENV_MEM_LAYOUT_SETTINGS \\\n+\t\"scriptaddr=0x60500000\\0\" \\\n+\t\"pxefile_addr_r=0x60600000\\0\" \\\n+\t\"fdt_addr_r=0x61f00000\\0\" \\\n+\t\"kernel_addr_r=0x62000000\\0\" \\\n+\t\"ramdisk_addr_r=0x64000000\\0\"\n+\n+#include \n+#define CONFIG_EXTRA_ENV_SETTINGS \\\n+\tENV_MEM_LAYOUT_SETTINGS \\\n+\t\"partitions=\" PARTS_DEFAULT \\\n+\tBOOTENV\n+\n+#endif\n+\n+#endif\n","prefixes":["U-Boot","2/8"]}