{"id":819116,"url":"http://patchwork.ozlabs.org/api/patches/819116/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/1506513517-25870-5-git-send-email-mmaddireddy@nvidia.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506513517-25870-5-git-send-email-mmaddireddy@nvidia.com>","list_archive_url":null,"date":"2017-09-27T11:58:37","name":"[V2,4/4] arm64: tegra: Enable PCIe on Jetson TX2","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"783ee30413040c0c672cbee01894b4c056dda72f","submitter":{"id":72399,"url":"http://patchwork.ozlabs.org/api/people/72399/?format=json","name":"Manikanta Maddireddy","email":"mmaddireddy@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/1506513517-25870-5-git-send-email-mmaddireddy@nvidia.com/mbox/","series":[{"id":5348,"url":"http://patchwork.ozlabs.org/api/series/5348/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=5348","date":"2017-09-27T11:58:34","name":"Add Tegra186 PCIe support","version":2,"mbox":"http://patchwork.ozlabs.org/series/5348/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/819116/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/819116/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2GdM3QcRz9tXn\n\tfor ;\n\tWed, 27 Sep 2017 22:01:43 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752794AbdI0MBj (ORCPT );\n\tWed, 27 Sep 2017 08:01:39 -0400","from hqemgate15.nvidia.com ([216.228.121.64]:13027 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752796AbdI0MBh (ORCPT\n\t); Wed, 27 Sep 2017 08:01:37 -0400","from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com\n\tid ; Wed, 27 Sep 2017 05:01:14 -0700","from HQMAIL105.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tWed, 27 Sep 2017 05:01:16 -0700","from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL105.nvidia.com\n\t(172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 27 Sep 2017 12:00:02 +0000","from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL102.nvidia.com\n\t(172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 27 Sep 2017 12:00:02 +0000","from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL102.nvidia.com\n\t(172.18.146.10) with Microsoft SMTP Server id 15.0.1293.2 via\n\tFrontend Transport; Wed, 27 Sep 2017 12:00:02 +0000","from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by\n\thqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150)\n\tid ; Wed, 27 Sep 2017 05:00:02 -0700"],"X-PGP-Universal":"processed;\n\tby hqpgpgate101.nvidia.com on Wed, 27 Sep 2017 05:01:16 -0700","From":"Manikanta Maddireddy ","To":", , ","CC":", ,\n\t, Manikanta Maddireddy ","Subject":"[PATCH V2 4/4] arm64: tegra: Enable PCIe on Jetson TX2","Date":"Wed, 27 Sep 2017 17:28:37 +0530","Message-ID":"<1506513517-25870-5-git-send-email-mmaddireddy@nvidia.com>","X-Mailer":"git-send-email 2.1.4","In-Reply-To":"<1506513517-25870-1-git-send-email-mmaddireddy@nvidia.com>","References":"<1506513517-25870-1-git-send-email-mmaddireddy@nvidia.com>","X-NVConfidentiality":"public","MIME-Version":"1.0","Content-Type":"text/plain","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"Enable x4 PCIe slot on Jetson TX2.\n\nSigned-off-by: Manikanta Maddireddy \nReviewed-by: Mikko Perttunen \nTested-by: Mikko Perttunen \n---\nV2: No change in this patch\n arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 24 ++++++++++++++++++++++++\n 1 file changed, 24 insertions(+)","diff":"diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi\nindex cf84d7046ad5..a4d96b2a23b4 100644\n--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi\n+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi\n@@ -378,4 +378,28 @@\n \t\t\tvin-supply = <&vdd_1v8>;\n \t\t};\n \t};\n+\n+\tpcie@10003000 {\n+\t\tstatus = \"okay\";\n+\n+\t\tdvdd-pex-supply = <&vdd_pex>;\n+\t\thvdd-pex-pll-supply = <&vdd_1v8>;\n+\t\thvdd-pex-supply = <&vdd_1v8>;\n+\t\tvddio-pexctl-aud-supply = <&vdd_1v8>;\n+\n+\t\tpci@1,0 {\n+\t\t\tnvidia,num-lanes = <4>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tpci@2,0 {\n+\t\t\tnvidia,num-lanes = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpci@3,0 {\n+\t\t\tnvidia,num-lanes = <1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n };\n","prefixes":["V2","4/4"]}