{"id":818936,"url":"http://patchwork.ozlabs.org/api/patches/818936/?format=json","web_url":"http://patchwork.ozlabs.org/project/sparclinux/patch/1506491952-9659-2-git-send-email-vijay.ac.kumar@oracle.com/","project":{"id":10,"url":"http://patchwork.ozlabs.org/api/projects/10/?format=json","name":"Linux SPARC Development ","link_name":"sparclinux","list_id":"sparclinux.vger.kernel.org","list_email":"sparclinux@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506491952-9659-2-git-send-email-vijay.ac.kumar@oracle.com>","list_archive_url":null,"date":"2017-09-27T05:59:11","name":"[1/2] sparc64: Define SPARC default fls and __fls","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"6d5a492488b7ac1052cee09b2ec35829154cac3e","submitter":{"id":67939,"url":"http://patchwork.ozlabs.org/api/people/67939/?format=json","name":"Vijay Kumar","email":"vijay.ac.kumar@oracle.com"},"delegate":{"id":34,"url":"http://patchwork.ozlabs.org/api/users/34/?format=json","username":"davem","first_name":"David","last_name":"Miller","email":"davem@davemloft.net"},"mbox":"http://patchwork.ozlabs.org/project/sparclinux/patch/1506491952-9659-2-git-send-email-vijay.ac.kumar@oracle.com/mbox/","series":[{"id":5285,"url":"http://patchwork.ozlabs.org/api/series/5285/?format=json","web_url":"http://patchwork.ozlabs.org/project/sparclinux/list/?series=5285","date":"2017-09-27T05:59:11","name":"sparc64: Optimize fls, fls64 and __fls","version":1,"mbox":"http://patchwork.ozlabs.org/series/5285/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/818936/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/818936/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=sparclinux-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y26bQ1Cs6z9t33\n\tfor ;\n\tWed, 27 Sep 2017 15:59:30 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752299AbdI0F73 (ORCPT );\n\tWed, 27 Sep 2017 01:59:29 -0400","from aserp1040.oracle.com ([141.146.126.69]:38409 \"EHLO\n\taserp1040.oracle.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752292AbdI0F71 (ORCPT\n\t); Wed, 27 Sep 2017 01:59:27 -0400","from aserv0022.oracle.com (aserv0022.oracle.com [141.146.126.234])\n\tby aserp1040.oracle.com (Sentrion-MTA-4.3.2/Sentrion-MTA-4.3.2)\n\twith ESMTP id v8R5xPo1006088\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256\n\tverify=OK); Wed, 27 Sep 2017 05:59:25 GMT","from userv0121.oracle.com (userv0121.oracle.com [156.151.31.72])\n\tby aserv0022.oracle.com (8.14.4/8.14.4) with ESMTP id v8R5xOS0021742\n\t(version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256\n\tverify=OK); Wed, 27 Sep 2017 05:59:24 GMT","from abhmp0012.oracle.com (abhmp0012.oracle.com [141.146.116.18])\n\tby userv0121.oracle.com (8.14.4/8.13.8) with ESMTP id\n\tv8R5xO8M005231; Wed, 27 Sep 2017 05:59:24 GMT","from ca-sparc60.us.oracle.com (/10.147.24.150)\n\tby default (Oracle Beehive Gateway v4.0)\n\twith ESMTP ; Tue, 26 Sep 2017 22:59:23 -0700"],"From":"Vijay Kumar ","To":"davem@davemloft.net","Cc":"linux-kernel@vger.kernel.org, sparclinux@vger.kernel.org,\n\tbabu.moger@oracle.com","Subject":"[PATCH 1/2] sparc64: Define SPARC default fls and __fls","Date":"Tue, 26 Sep 2017 23:59:11 -0600","Message-Id":"<1506491952-9659-2-git-send-email-vijay.ac.kumar@oracle.com>","X-Mailer":"git-send-email 1.7.1","In-Reply-To":"<1506491952-9659-1-git-send-email-vijay.ac.kumar@oracle.com>","References":"<1506491952-9659-1-git-send-email-vijay.ac.kumar@oracle.com>","X-Source-IP":"aserv0022.oracle.com [141.146.126.234]","Sender":"sparclinux-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"sparclinux@vger.kernel.org"},"content":"fls and __fls will now require boot time patching on T4\nand above. Redefining these functions under arc/sparc/lib.\n\nSigned-off-by: Vijay Kumar \nReviewed-by: Babu Moger \n---\n arch/sparc/include/asm/bitops_64.h | 7 +-\n arch/sparc/lib/Makefile | 1 +\n arch/sparc/lib/fls.S | 126 ++++++++++++++++++++++++++++++++++++\n 3 files changed, 131 insertions(+), 3 deletions(-)","diff":"diff --git a/arch/sparc/include/asm/bitops_64.h b/arch/sparc/include/asm/bitops_64.h\nindex 2d52240..946c236 100644\n--- a/arch/sparc/include/asm/bitops_64.h\n+++ b/arch/sparc/include/asm/bitops_64.h\n@@ -22,11 +22,12 @@\n void clear_bit(unsigned long nr, volatile unsigned long *addr);\n void change_bit(unsigned long nr, volatile unsigned long *addr);\n \n+#define fls64(word) (((word)?(__fls(word) + 1):0))\n+int fls(unsigned int word);\n+int __fls(unsigned long word);\n+\n #include \n \n-#include \n-#include \n-#include \n \n #ifdef __KERNEL__\n \ndiff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile\nindex 07c03e7..eefbb9c 100644\n--- a/arch/sparc/lib/Makefile\n+++ b/arch/sparc/lib/Makefile\n@@ -16,6 +16,7 @@ lib-$(CONFIG_SPARC64) += atomic_64.o\n lib-$(CONFIG_SPARC32) += lshrdi3.o ashldi3.o\n lib-$(CONFIG_SPARC32) += muldi3.o bitext.o cmpdi2.o\n lib-$(CONFIG_SPARC64) += multi3.o\n+lib-$(CONFIG_SPARC64) += fls.o\n \n lib-$(CONFIG_SPARC64) += copy_page.o clear_page.o bzero.o\n lib-$(CONFIG_SPARC64) += csum_copy.o csum_copy_from_user.o csum_copy_to_user.o\ndiff --git a/arch/sparc/lib/fls.S b/arch/sparc/lib/fls.S\nnew file mode 100644\nindex 0000000..a19bff2\n--- /dev/null\n+++ b/arch/sparc/lib/fls.S\n@@ -0,0 +1,126 @@\n+/* fls.S: SPARC default fls and __fls definitions.\n+ *\n+ * SPARC default fls and __fls definitions, which follows the same\n+ * algorithm as in generic fls() and __fls(). These functions will\n+ * be boot time patched on T4 and onward.\n+ */\n+\n+#include \n+#include \n+\n+\t.text\n+\t.align\t32\n+\n+\t.global\tfls, __fls\n+\t.type\tfls,\t#function\n+\t.type\t__fls,\t#function\n+\n+\t.register\t%g2, #scratch\n+\t.register\t%g3, #scratch\n+\n+EXPORT_SYMBOL(__fls)\n+EXPORT_SYMBOL(fls)\n+\n+fls:\n+\tbrz,pn\t%o0, 6f\n+\t mov\t0, %o1\n+\tsethi\t%hi(0xffff0000), %g3\n+\tmov\t%o0, %g2\n+\tandcc\t%o0, %g3, %g0\n+\tbe,pt\t%icc, 8f\n+\t mov\t32, %o1\n+\tsethi\t%hi(0xff000000), %g3\n+\tandcc\t%g2, %g3, %g0\n+\tbne,pt\t%icc, 3f\n+\t sethi\t%hi(0xf0000000), %g3\n+\tsll\t%o0, 8, %o0\n+1:\n+\tadd\t%o1, -8, %o1\n+\tsra\t%o0, 0, %o0\n+\tmov\t%o0, %g2\n+2:\n+\tsethi\t%hi(0xf0000000), %g3\n+3:\n+\tandcc\t%g2, %g3, %g0\n+\tbne,pt\t%icc, 4f\n+\t sethi\t%hi(0xc0000000), %g3\n+\tsll\t%o0, 4, %o0\n+\tadd\t%o1, -4, %o1\n+\tsra\t%o0, 0, %o0\n+\tmov\t%o0, %g2\n+4:\n+\tandcc\t%g2, %g3, %g0\n+\tbe,a,pt\t%icc, 7f\n+\t sll\t%o0, 2, %o0\n+5:\n+\txnor\t%g0, %o0, %o0\n+\tsrl\t%o0, 31, %o0\n+\tsub\t%o1, %o0, %o1\n+6:\n+\tjmp\t%o7 + 8\n+\t sra\t%o1, 0, %o0\n+7:\n+\tadd\t%o1, -2, %o1\n+\tba,pt\t%xcc, 5b\n+\t sra\t%o0, 0, %o0\n+8:\n+\tsll\t%o0, 16, %o0\n+\tsethi\t%hi(0xff000000), %g3\n+\tsra\t%o0, 0, %o0\n+\tmov\t%o0, %g2\n+\tandcc\t%g2, %g3, %g0\n+\tbne,pt\t%icc, 2b\n+\t mov\t16, %o1\n+\tba,pt\t%xcc, 1b\n+\t sll\t%o0, 8, %o0\n+\t.size\tfls, .-fls\n+\n+__fls:\n+#if BITS_PER_LONG == 64\n+\tmov\t-1, %g2\n+\tsllx\t%g2, 32, %g2\n+\tand\t%o0, %g2, %g2\n+\tbrnz,pt\t%g2, 1f\n+\t mov\t63, %g1\n+\tsllx\t%o0, 32, %o0\n+#endif\n+\tmov\t31, %g1\n+1:\n+\tmov\t-1, %g2\n+\tsllx\t%g2, (BITS_PER_LONG-16), %g2\n+\tand\t%o0, %g2, %g2\n+\tbrnz,pt\t%g2, 2f\n+\t mov\t-1, %g2\n+\tsllx\t%o0, 16, %o0\n+\tadd\t%g1, -16, %g1\n+2:\n+\tmov\t-1, %g2\n+\tsllx\t%g2, (BITS_PER_LONG-8), %g2\n+\tand\t%o0, %g2, %g2\n+\tbrnz,pt\t%g2, 3f\n+\t mov\t-1, %g2\n+\tsllx\t%o0, 8, %o0\n+\tadd\t%g1, -8, %g1\n+3:\n+\tsllx\t%g2, (BITS_PER_LONG-4), %g2\n+\tand\t%o0, %g2, %g2\n+\tbrnz,pt\t%g2, 4f\n+\t mov\t-1, %g2\n+\tsllx\t%o0, 4, %o0\n+\tadd\t%g1, -4, %g1\n+4:\n+\tsllx\t%g2, (BITS_PER_LONG-2), %g2\n+\tand\t%o0, %g2, %g2\n+\tbrnz,pt\t%g2, 5f\n+\t mov\t-1, %g3\n+\tsllx\t%o0, 2, %o0\n+\tadd\t%g1, -2, %g1\n+5:\n+\tmov\t0, %g2\n+\tsllx\t%g3, (BITS_PER_LONG-1), %g3\n+\tand\t%o0, %g3, %o0\n+\tmovre\t%o0, 1, %g2\n+\tsub\t%g1, %g2, %g1\n+\tjmp\t%o7+8\n+\t sra\t%g1, 0, %o0\n+\t.size\t__fls, .-__fls\n","prefixes":["1/2"]}