{"id":818809,"url":"http://patchwork.ozlabs.org/api/patches/818809/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170926201427.2833-2-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170926201427.2833-2-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-26T20:14:19","name":"[v3,1/9] target/i386: Convert to disas_set_info hook","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"900340bd97ebe08eb393150a451129ed2befd8c2","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170926201427.2833-2-richard.henderson@linaro.org/mbox/","series":[{"id":5223,"url":"http://patchwork.ozlabs.org/api/series/5223/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=5223","date":"2017-09-26T20:14:18","name":"Support the Capstone disassembler","version":3,"mbox":"http://patchwork.ozlabs.org/series/5223/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/818809/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/818809/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c05::235","Subject":"[Qemu-devel] [PATCH v3 1/9] target/i386: Convert to disas_set_info\n\thook","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, qemu-ppc@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Reviewed-by: Alex Bennée \nSigned-off-by: Richard Henderson \n---\n disas.c | 22 ++--------------------\n monitor.c | 21 ---------------------\n target/i386/cpu.c | 12 ++++++++++++\n target/i386/translate.c | 8 +-------\n 4 files changed, 15 insertions(+), 48 deletions(-)","diff":"diff --git a/disas.c b/disas.c\nindex d6a1eb9c8e..2be716fdb2 100644\n--- a/disas.c\n+++ b/disas.c\n@@ -205,16 +205,7 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,\n cc->disas_set_info(cpu, &s.info);\n }\n \n-#if defined(TARGET_I386)\n- if (flags == 2) {\n- s.info.mach = bfd_mach_x86_64;\n- } else if (flags == 1) {\n- s.info.mach = bfd_mach_i386_i8086;\n- } else {\n- s.info.mach = bfd_mach_i386_i386;\n- }\n- s.info.print_insn = print_insn_i386;\n-#elif defined(TARGET_PPC)\n+#if defined(TARGET_PPC)\n if ((flags >> 16) & 1) {\n s.info.endian = BFD_ENDIAN_LITTLE;\n }\n@@ -390,16 +381,7 @@ void monitor_disas(Monitor *mon, CPUState *cpu,\n cc->disas_set_info(cpu, &s.info);\n }\n \n-#if defined(TARGET_I386)\n- if (flags == 2) {\n- s.info.mach = bfd_mach_x86_64;\n- } else if (flags == 1) {\n- s.info.mach = bfd_mach_i386_i8086;\n- } else {\n- s.info.mach = bfd_mach_i386_i386;\n- }\n- s.info.print_insn = print_insn_i386;\n-#elif defined(TARGET_PPC)\n+#if defined(TARGET_PPC)\n if (flags & 0xFFFF) {\n /* If we have a precise definition of the instruction set, use it. */\n s.info.mach = flags & 0xFFFF;\ndiff --git a/monitor.c b/monitor.c\nindex f4856b9268..1184bec678 100644\n--- a/monitor.c\n+++ b/monitor.c\n@@ -1310,27 +1310,6 @@ static void memory_dump(Monitor *mon, int count, int format, int wsize,\n \n if (format == 'i') {\n int flags = 0;\n-#ifdef TARGET_I386\n- CPUArchState *env = mon_get_cpu_env();\n- if (wsize == 2) {\n- flags = 1;\n- } else if (wsize == 4) {\n- flags = 0;\n- } else {\n- /* as default we use the current CS size */\n- flags = 0;\n- if (env) {\n-#ifdef TARGET_X86_64\n- if ((env->efer & MSR_EFER_LMA) &&\n- (env->segs[R_CS].flags & DESC_L_MASK))\n- flags = 2;\n- else\n-#endif\n- if (!(env->segs[R_CS].flags & DESC_B_MASK))\n- flags = 1;\n- }\n- }\n-#endif\n #ifdef TARGET_PPC\n CPUArchState *env = mon_get_cpu_env();\n flags = msr_le << 16;\ndiff --git a/target/i386/cpu.c b/target/i386/cpu.c\nindex 98732cd65f..13b2f8fbc5 100644\n--- a/target/i386/cpu.c\n+++ b/target/i386/cpu.c\n@@ -4097,6 +4097,17 @@ static bool x86_cpu_has_work(CPUState *cs)\n !(env->hflags & HF_SMM_MASK));\n }\n \n+static void x86_disas_set_info(CPUState *cs, disassemble_info *info)\n+{\n+ X86CPU *cpu = X86_CPU(cs);\n+ CPUX86State *env = &cpu->env;\n+\n+ info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64\n+ : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386\n+ : bfd_mach_i386_i8086);\n+ info->print_insn = print_insn_i386;\n+}\n+\n static Property x86_cpu_properties[] = {\n #ifdef CONFIG_USER_ONLY\n /* apic_id = 0 by default for *-user, see commit 9886e834 */\n@@ -4216,6 +4227,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)\n #endif\n cc->cpu_exec_enter = x86_cpu_exec_enter;\n cc->cpu_exec_exit = x86_cpu_exec_exit;\n+ cc->disas_set_info = x86_disas_set_info;\n \n dc->user_creatable = true;\n }\ndiff --git a/target/i386/translate.c b/target/i386/translate.c\nindex a8986f4c1a..9932d64f2e 100644\n--- a/target/i386/translate.c\n+++ b/target/i386/translate.c\n@@ -8527,15 +8527,9 @@ static void i386_tr_disas_log(const DisasContextBase *dcbase,\n CPUState *cpu)\n {\n DisasContext *dc = container_of(dcbase, DisasContext, base);\n- int disas_flags = !dc->code32;\n \n qemu_log(\"IN: %s\\n\", lookup_symbol(dc->base.pc_first));\n-#ifdef TARGET_X86_64\n- if (dc->code64) {\n- disas_flags = 2;\n- }\n-#endif\n- log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, disas_flags);\n+ log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, 0);\n }\n \n static const TranslatorOps i386_tr_ops = {\n","prefixes":["v3","1/9"]}