{"id":818590,"url":"http://patchwork.ozlabs.org/api/patches/818590/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/150642407216.3900.10726526729124062497.stgit@Misha-PC.lan02.inno/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<150642407216.3900.10726526729124062497.stgit@Misha-PC.lan02.inno>","list_archive_url":null,"date":"2017-09-26T11:07:52","name":"[40/43] windbg: implemented kd_api_read_msr and kd_api_write_msr","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e6556a389a59bb2a876fbb17ddc87cb25eef411d","submitter":{"id":71645,"url":"http://patchwork.ozlabs.org/api/people/71645/?format=json","name":"Mikhail Abakumov","email":"mikhail.abakumov@ispras.ru"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/150642407216.3900.10726526729124062497.stgit@Misha-PC.lan02.inno/mbox/","series":[{"id":5104,"url":"http://patchwork.ozlabs.org/api/series/5104/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=5104","date":"2017-09-26T11:04:06","name":"Windbg supporting","version":1,"mbox":"http://patchwork.ozlabs.org/series/5104/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/818590/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/818590/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y1fDg1gDPz9t49\n\tfor ;\n\tTue, 26 Sep 2017 21:41:38 +1000 (AEST)","from localhost ([::1]:46912 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dwoF5-0001zE-Da\n\tfor incoming@patchwork.ozlabs.org; Tue, 26 Sep 2017 07:41:35 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:60413)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dwnib-0006EC-E5\n\tfor qemu-devel@nongnu.org; Tue, 26 Sep 2017 07:08:06 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dwniU-0001o1-PH\n\tfor qemu-devel@nongnu.org; Tue, 26 Sep 2017 07:08:01 -0400","from mail.ispras.ru ([83.149.199.45]:52432)\n\tby eggs.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dwniU-0001nb-DA\n\tfor qemu-devel@nongnu.org; Tue, 26 Sep 2017 07:07:54 -0400","from Misha-PC.lan02.inno (unknown [85.142.117.226])\n\tby mail.ispras.ru (Postfix) with ESMTPSA id B4D5A540111;\n\tTue, 26 Sep 2017 14:07:53 +0300 (MSK)"],"From":"Mihail Abakumov ","To":"qemu-devel@nongnu.org","Date":"Tue, 26 Sep 2017 14:07:52 +0300","Message-ID":"<150642407216.3900.10726526729124062497.stgit@Misha-PC.lan02.inno>","In-Reply-To":"<150642384156.3900.3326424823772221077.stgit@Misha-PC.lan02.inno>","References":"<150642384156.3900.3326424823772221077.stgit@Misha-PC.lan02.inno>","User-Agent":"StGit/0.17.1-dirty","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 3.x [fuzzy]","X-Received-From":"83.149.199.45","Subject":"[Qemu-devel] [PATCH 40/43] windbg: implemented kd_api_read_msr and\n\tkd_api_write_msr","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"sw@weilnetz.de, lprosek@redhat.com, dovgaluk@ispras.ru,\n\trkagan@virtuozzo.com, pbonzini@redhat.com, den@openvz.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Signed-off-by: Mihail Abakumov \nSigned-off-by: Pavel Dovgalyuk \nSigned-off-by: Dmitriy Koltunov \n---\n include/exec/windbgstub-utils.h | 2 \n windbgstub-utils.c | 319 +++++++++++++++++++++++++++++++++++++++\n windbgstub.c | 8 +\n 3 files changed, 329 insertions(+)","diff":"diff --git a/include/exec/windbgstub-utils.h b/include/exec/windbgstub-utils.h\nindex e76bf1ad6f..23cafb1a89 100755\n--- a/include/exec/windbgstub-utils.h\n+++ b/include/exec/windbgstub-utils.h\n@@ -116,6 +116,8 @@ void kd_api_write_io_space(CPUState *cpu, PacketData *pd);\n void kd_api_read_physical_memory(CPUState *cpu, PacketData *pd);\n void kd_api_write_physical_memory(CPUState *cpu, PacketData *pd);\n void kd_api_get_version(CPUState *cpu, PacketData *pd);\n+void kd_api_read_msr(CPUState *cpu, PacketData *pd);\n+void kd_api_write_msr(CPUState *cpu, PacketData *pd);\n void kd_api_unsupported(CPUState *cpu, PacketData *pd);\n \n SizedBuf kd_gen_exception_sc(CPUState *cpu);\ndiff --git a/windbgstub-utils.c b/windbgstub-utils.c\nindex 171097eba2..26bdb1f6ea 100755\n--- a/windbgstub-utils.c\n+++ b/windbgstub-utils.c\n@@ -1221,6 +1221,325 @@ void kd_api_get_version(CPUState *cpu, PacketData *pd)\n }\n }\n \n+void kd_api_read_msr(CPUState *cpu, PacketData *pd)\n+{\n+ DBGKD_READ_WRITE_MSR *m64c = &pd->m64.u.ReadWriteMsr;\n+ CPUArchState *env = cpu->env_ptr;\n+\n+ uint64_t val;\n+\n+ cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0, 0);\n+\n+ switch ((uint32_t)env->regs[R_ECX]) {\n+ case MSR_IA32_SYSENTER_CS:\n+ val = env->sysenter_cs;\n+ break;\n+ case MSR_IA32_SYSENTER_ESP:\n+ val = env->sysenter_esp;\n+ break;\n+ case MSR_IA32_SYSENTER_EIP:\n+ val = env->sysenter_eip;\n+ break;\n+ case MSR_IA32_APICBASE:\n+ val = cpu_get_apic_base(x86_env_get_cpu(env)->apic_state);\n+ break;\n+ case MSR_EFER:\n+ val = env->efer;\n+ break;\n+ case MSR_STAR:\n+ val = env->star;\n+ break;\n+ case MSR_PAT:\n+ val = env->pat;\n+ break;\n+ case MSR_VM_HSAVE_PA:\n+ val = env->vm_hsave;\n+ break;\n+ case MSR_IA32_PERF_STATUS:\n+ /* tsc_increment_by_tick */\n+ val = 1000ULL;\n+ /* CPU multiplier */\n+ val |= (((uint64_t)4ULL) << 40);\n+ break;\n+#ifdef TARGET_X86_64\n+ case MSR_LSTAR:\n+ val = env->lstar;\n+ break;\n+ case MSR_CSTAR:\n+ val = env->cstar;\n+ break;\n+ case MSR_FMASK:\n+ val = env->fmask;\n+ break;\n+ case MSR_FSBASE:\n+ val = env->segs[R_FS].base;\n+ break;\n+ case MSR_GSBASE:\n+ val = env->segs[R_GS].base;\n+ break;\n+ case MSR_KERNELGSBASE:\n+ val = env->kernelgsbase;\n+ break;\n+ case MSR_TSC_AUX:\n+ val = env->tsc_aux;\n+ break;\n+#endif\n+ case MSR_MTRRphysBase(0):\n+ case MSR_MTRRphysBase(1):\n+ case MSR_MTRRphysBase(2):\n+ case MSR_MTRRphysBase(3):\n+ case MSR_MTRRphysBase(4):\n+ case MSR_MTRRphysBase(5):\n+ case MSR_MTRRphysBase(6):\n+ case MSR_MTRRphysBase(7):\n+ val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -\n+ MSR_MTRRphysBase(0)) / 2].base;\n+ break;\n+ case MSR_MTRRphysMask(0):\n+ case MSR_MTRRphysMask(1):\n+ case MSR_MTRRphysMask(2):\n+ case MSR_MTRRphysMask(3):\n+ case MSR_MTRRphysMask(4):\n+ case MSR_MTRRphysMask(5):\n+ case MSR_MTRRphysMask(6):\n+ case MSR_MTRRphysMask(7):\n+ val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -\n+ MSR_MTRRphysMask(0)) / 2].mask;\n+ break;\n+ case MSR_MTRRfix64K_00000:\n+ val = env->mtrr_fixed[0];\n+ break;\n+ case MSR_MTRRfix16K_80000:\n+ case MSR_MTRRfix16K_A0000:\n+ val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -\n+ MSR_MTRRfix16K_80000 + 1];\n+ break;\n+ case MSR_MTRRfix4K_C0000:\n+ case MSR_MTRRfix4K_C8000:\n+ case MSR_MTRRfix4K_D0000:\n+ case MSR_MTRRfix4K_D8000:\n+ case MSR_MTRRfix4K_E0000:\n+ case MSR_MTRRfix4K_E8000:\n+ case MSR_MTRRfix4K_F0000:\n+ case MSR_MTRRfix4K_F8000:\n+ val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -\n+ MSR_MTRRfix4K_C0000 + 3];\n+ break;\n+ case MSR_MTRRdefType:\n+ val = env->mtrr_deftype;\n+ break;\n+ case MSR_MTRRcap:\n+ if (env->features[FEAT_1_EDX] & CPUID_MTRR) {\n+ val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT |\n+ MSR_MTRRcap_WC_SUPPORTED;\n+ } else {\n+ /* XXX: exception? */\n+ val = 0;\n+ }\n+ break;\n+ case MSR_MCG_CAP:\n+ val = env->mcg_cap;\n+ break;\n+ case MSR_MCG_CTL:\n+ if (env->mcg_cap & MCG_CTL_P) {\n+ val = env->mcg_ctl;\n+ } else {\n+ val = 0;\n+ }\n+ break;\n+ case MSR_MCG_STATUS:\n+ val = env->mcg_status;\n+ break;\n+ case MSR_IA32_MISC_ENABLE:\n+ val = env->msr_ia32_misc_enable;\n+ break;\n+ case MSR_IA32_BNDCFGS:\n+ val = env->msr_bndcfgs;\n+ break;\n+ default:\n+ if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL\n+ && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +\n+ (4 * env->mcg_cap & 0xff)) {\n+ uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;\n+ val = env->mce_banks[offset];\n+ break;\n+ }\n+ /* XXX: exception? */\n+ val = 0;\n+ break;\n+ }\n+\n+ val = ldq_p(&val);\n+ m64c->DataValueLow = UINT32_P(val)[0];\n+ m64c->DataValueHigh = UINT32_P(val)[1];\n+ pd->m64.ReturnStatus = STATUS_SUCCESS;\n+}\n+\n+void kd_api_write_msr(CPUState *cpu, PacketData *pd)\n+{\n+ DBGKD_READ_WRITE_MSR *m64c = &pd->m64.u.ReadWriteMsr;\n+ CPUArchState *env = cpu->env_ptr;\n+\n+ uint64_t val;\n+\n+ cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, 0);\n+\n+ val = m64c->DataValueLow | ((uint64_t) m64c->DataValueHigh) << 32;\n+ val = ldq_p(&val);\n+\n+ switch ((uint32_t)env->regs[R_ECX]) {\n+ case MSR_IA32_SYSENTER_CS:\n+ env->sysenter_cs = val & 0xffff;\n+ break;\n+ case MSR_IA32_SYSENTER_ESP:\n+ env->sysenter_esp = val;\n+ break;\n+ case MSR_IA32_SYSENTER_EIP:\n+ env->sysenter_eip = val;\n+ break;\n+ case MSR_IA32_APICBASE:\n+ cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val);\n+ break;\n+ case MSR_EFER:\n+ {\n+ uint64_t update_mask;\n+\n+ update_mask = 0;\n+ if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) {\n+ update_mask |= MSR_EFER_SCE;\n+ }\n+ if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {\n+ update_mask |= MSR_EFER_LME;\n+ }\n+ if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {\n+ update_mask |= MSR_EFER_FFXSR;\n+ }\n+ if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) {\n+ update_mask |= MSR_EFER_NXE;\n+ }\n+ if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {\n+ update_mask |= MSR_EFER_SVME;\n+ }\n+ if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {\n+ update_mask |= MSR_EFER_FFXSR;\n+ }\n+ cpu_load_efer(env, (env->efer & ~update_mask) |\n+ (val & update_mask));\n+ }\n+ break;\n+ case MSR_STAR:\n+ env->star = val;\n+ break;\n+ case MSR_PAT:\n+ env->pat = val;\n+ break;\n+ case MSR_VM_HSAVE_PA:\n+ env->vm_hsave = val;\n+ break;\n+#ifdef TARGET_X86_64\n+ case MSR_LSTAR:\n+ env->lstar = val;\n+ break;\n+ case MSR_CSTAR:\n+ env->cstar = val;\n+ break;\n+ case MSR_FMASK:\n+ env->fmask = val;\n+ break;\n+ case MSR_FSBASE:\n+ env->segs[R_FS].base = val;\n+ break;\n+ case MSR_GSBASE:\n+ env->segs[R_GS].base = val;\n+ break;\n+ case MSR_KERNELGSBASE:\n+ env->kernelgsbase = val;\n+ break;\n+#endif\n+ case MSR_MTRRphysBase(0):\n+ case MSR_MTRRphysBase(1):\n+ case MSR_MTRRphysBase(2):\n+ case MSR_MTRRphysBase(3):\n+ case MSR_MTRRphysBase(4):\n+ case MSR_MTRRphysBase(5):\n+ case MSR_MTRRphysBase(6):\n+ case MSR_MTRRphysBase(7):\n+ env->mtrr_var[((uint32_t)env->regs[R_ECX] -\n+ MSR_MTRRphysBase(0)) / 2].base = val;\n+ break;\n+ case MSR_MTRRphysMask(0):\n+ case MSR_MTRRphysMask(1):\n+ case MSR_MTRRphysMask(2):\n+ case MSR_MTRRphysMask(3):\n+ case MSR_MTRRphysMask(4):\n+ case MSR_MTRRphysMask(5):\n+ case MSR_MTRRphysMask(6):\n+ case MSR_MTRRphysMask(7):\n+ env->mtrr_var[((uint32_t)env->regs[R_ECX] -\n+ MSR_MTRRphysMask(0)) / 2].mask = val;\n+ break;\n+ case MSR_MTRRfix64K_00000:\n+ env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -\n+ MSR_MTRRfix64K_00000] = val;\n+ break;\n+ case MSR_MTRRfix16K_80000:\n+ case MSR_MTRRfix16K_A0000:\n+ env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -\n+ MSR_MTRRfix16K_80000 + 1] = val;\n+ break;\n+ case MSR_MTRRfix4K_C0000:\n+ case MSR_MTRRfix4K_C8000:\n+ case MSR_MTRRfix4K_D0000:\n+ case MSR_MTRRfix4K_D8000:\n+ case MSR_MTRRfix4K_E0000:\n+ case MSR_MTRRfix4K_E8000:\n+ case MSR_MTRRfix4K_F0000:\n+ case MSR_MTRRfix4K_F8000:\n+ env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -\n+ MSR_MTRRfix4K_C0000 + 3] = val;\n+ break;\n+ case MSR_MTRRdefType:\n+ env->mtrr_deftype = val;\n+ break;\n+ case MSR_MCG_STATUS:\n+ env->mcg_status = val;\n+ break;\n+ case MSR_MCG_CTL:\n+ if ((env->mcg_cap & MCG_CTL_P)\n+ && (val == 0 || val == ~(uint64_t)0)) {\n+ env->mcg_ctl = val;\n+ }\n+ break;\n+ case MSR_TSC_AUX:\n+ env->tsc_aux = val;\n+ break;\n+ case MSR_IA32_MISC_ENABLE:\n+ env->msr_ia32_misc_enable = val;\n+ break;\n+ case MSR_IA32_BNDCFGS:\n+ /* FIXME: #GP if reserved bits are set. */\n+ /* FIXME: Extend highest implemented bit of linear address. */\n+ env->msr_bndcfgs = val;\n+ cpu_sync_bndcs_hflags(env);\n+ break;\n+ default:\n+ if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL\n+ && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +\n+ (4 * env->mcg_cap & 0xff)) {\n+ uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;\n+ if ((offset & 0x3) != 0\n+ || (val == 0 || val == ~(uint64_t)0)) {\n+ env->mce_banks[offset] = val;\n+ }\n+ break;\n+ }\n+ /* XXX: exception? */\n+ break;\n+ }\n+\n+ pd->m64.ReturnStatus = STATUS_SUCCESS;\n+}\n+\n void kd_api_unsupported(CPUState *cpu, PacketData *pd)\n {\n WINDBG_ERROR(\"Catched unimplemented api %s\",\ndiff --git a/windbgstub.c b/windbgstub.c\nindex b37393d93c..1ec4932ddc 100755\n--- a/windbgstub.c\n+++ b/windbgstub.c\n@@ -190,6 +190,14 @@ static void windbg_process_manipulate_packet(ParsingContext *ctx)\n kd_api_write_physical_memory(cpu, &ctx->data);\n break;\n \n+ case DbgKdReadMachineSpecificRegister:\n+ kd_api_read_msr(cpu, &ctx->data);\n+ break;\n+\n+ case DbgKdWriteMachineSpecificRegister:\n+ kd_api_write_msr(cpu, &ctx->data);\n+ break;\n+\n case DbgKdGetVersionApi:\n kd_api_get_version(cpu, &ctx->data);\n break;\n","prefixes":["40/43"]}