{"id":818570,"url":"http://patchwork.ozlabs.org/api/patches/818570/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/150642397488.3900.828583173542559010.stgit@Misha-PC.lan02.inno/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<150642397488.3900.828583173542559010.stgit@Misha-PC.lan02.inno>","list_archive_url":null,"date":"2017-09-26T11:06:15","name":"[23/43] windbg: kernel's structures","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"79773e5d375dccb4d22ebc9728f27e542dd32c54","submitter":{"id":71645,"url":"http://patchwork.ozlabs.org/api/people/71645/?format=json","name":"Mikhail Abakumov","email":"mikhail.abakumov@ispras.ru"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/150642397488.3900.828583173542559010.stgit@Misha-PC.lan02.inno/mbox/","series":[{"id":5104,"url":"http://patchwork.ozlabs.org/api/series/5104/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=5104","date":"2017-09-26T11:04:06","name":"Windbg supporting","version":1,"mbox":"http://patchwork.ozlabs.org/series/5104/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/818570/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/818570/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y1dy41JmWz9tXP\n\tfor ;\n\tTue, 26 Sep 2017 21:29:00 +1000 (AEST)","from localhost ([::1]:46805 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dwo2s-0007OJ-4C\n\tfor incoming@patchwork.ozlabs.org; Tue, 26 Sep 2017 07:28:58 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:59640)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dwngx-0004fJ-1R\n\tfor qemu-devel@nongnu.org; Tue, 26 Sep 2017 07:06:20 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dwngv-0001Ao-I2\n\tfor qemu-devel@nongnu.org; Tue, 26 Sep 2017 07:06:19 -0400","from mail.ispras.ru ([83.149.199.45]:52072)\n\tby eggs.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dwngv-0001AO-5C\n\tfor qemu-devel@nongnu.org; Tue, 26 Sep 2017 07:06:17 -0400","from Misha-PC.lan02.inno (unknown [85.142.117.226])\n\tby mail.ispras.ru (Postfix) with ESMTPSA id 6E9135400CF;\n\tTue, 26 Sep 2017 14:06:16 +0300 (MSK)"],"From":"Mihail Abakumov ","To":"qemu-devel@nongnu.org","Date":"Tue, 26 Sep 2017 14:06:15 +0300","Message-ID":"<150642397488.3900.828583173542559010.stgit@Misha-PC.lan02.inno>","In-Reply-To":"<150642384156.3900.3326424823772221077.stgit@Misha-PC.lan02.inno>","References":"<150642384156.3900.3326424823772221077.stgit@Misha-PC.lan02.inno>","User-Agent":"StGit/0.17.1-dirty","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 3.x [fuzzy]","X-Received-From":"83.149.199.45","Subject":"[Qemu-devel] [PATCH 23/43] windbg: kernel's structures","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"sw@weilnetz.de, lprosek@redhat.com, dovgaluk@ispras.ru,\n\trkagan@virtuozzo.com, pbonzini@redhat.com, den@openvz.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Defined Windows kernel's structures (CPU_CONTEXT and CPU_KSPECIAL_REGISTERS) for i386 and x64_86.\n\nSigned-off-by: Mihail Abakumov \nSigned-off-by: Pavel Dovgalyuk \nSigned-off-by: Dmitriy Koltunov \n---\n windbgstub-utils.c | 247 ++++++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 247 insertions(+)","diff":"diff --git a/windbgstub-utils.c b/windbgstub-utils.c\nindex 1bde60a1e9..3c81ecefb8 100755\n--- a/windbgstub-utils.c\n+++ b/windbgstub-utils.c\n@@ -23,6 +23,253 @@\n # define OFFSET_KPRCB_CURRTHREAD 0x4\n #endif\n \n+/*\n+ * Next code copied from winnt.h\n+ */\n+#ifdef TARGET_X86_64\n+\n+#define CPU_CONTEXT_AMD64 0x100000\n+\n+#define CPU_CONTEXT_CONTROL (CPU_CONTEXT_AMD64 | 0x1)\n+#define CPU_CONTEXT_INTEGER (CPU_CONTEXT_AMD64 | 0x2)\n+#define CPU_CONTEXT_SEGMENTS (CPU_CONTEXT_AMD64 | 0x4)\n+#define CPU_CONTEXT_FLOATING_POINT (CPU_CONTEXT_AMD64 | 0x8)\n+#define CPU_CONTEXT_DEBUG_REGISTERS (CPU_CONTEXT_AMD64 | 0x10)\n+\n+#define CPU_CONTEXT_FULL \\\n+ (CPU_CONTEXT_CONTROL | CPU_CONTEXT_INTEGER | CPU_CONTEXT_FLOATING_POINT)\n+#define CPU_CONTEXT_ALL \\\n+ (CPU_CONTEXT_FULL | CPU_CONTEXT_SEGMENTS | CPU_CONTEXT_DEBUG_REGISTERS)\n+\n+typedef struct _CPU_DESCRIPTOR {\n+ uint16_t Pad[3];\n+ uint16_t Limit;\n+ uint64_t Base;\n+} CPU_DESCRIPTOR, *PCPU_DESCRIPTOR;\n+\n+typedef struct _CPU_KSPECIAL_REGISTERS {\n+ uint64_t Cr0;\n+ uint64_t Cr2;\n+ uint64_t Cr3;\n+ uint64_t Cr4;\n+ uint64_t KernelDr0;\n+ uint64_t KernelDr1;\n+ uint64_t KernelDr2;\n+ uint64_t KernelDr3;\n+ uint64_t KernelDr6;\n+ uint64_t KernelDr7;\n+ CPU_DESCRIPTOR Gdtr;\n+ CPU_DESCRIPTOR Idtr;\n+ uint16_t Tr;\n+ uint16_t Ldtr;\n+ uint32_t MxCsr;\n+ uint64_t DebugControl;\n+ uint64_t LastBranchToRip;\n+ uint64_t LastBranchFromRip;\n+ uint64_t LastExceptionToRip;\n+ uint64_t LastExceptionFromRip;\n+ uint64_t Cr8;\n+ uint64_t MsrGsBase;\n+ uint64_t MsrGsSwap;\n+ uint64_t MsrStar;\n+ uint64_t MsrLStar;\n+ uint64_t MsrCStar;\n+ uint64_t MsrSyscallMask;\n+ uint64_t Xcr0;\n+} CPU_KSPECIAL_REGISTERS, *PCPU_KSPECIAL_REGISTERS;\n+\n+#pragma pack(push, 2)\n+typedef struct _CPU_M128A {\n+ uint64_t Low;\n+ int64_t High;\n+} CPU_M128A, *PCPU_M128A;\n+#pragma pack(pop)\n+\n+typedef struct _CPU_XMM_SAVE_AREA32 {\n+ uint16_t ControlWord;\n+ uint16_t StatusWord;\n+ uint8_t TagWord;\n+ uint8_t Reserved1;\n+ uint16_t ErrorOpcode;\n+ uint32_t ErrorOffset;\n+ uint16_t ErrorSelector;\n+ uint16_t Reserved2;\n+ uint32_t DataOffset;\n+ uint16_t DataSelector;\n+ uint16_t Reserved3;\n+ uint32_t MxCsr;\n+ uint32_t MxCsr_Mask;\n+ CPU_M128A FloatRegisters[8];\n+ CPU_M128A XmmRegisters[16];\n+ uint8_t Reserved4[96];\n+} CPU_XMM_SAVE_AREA32, *PCPU_XMM_SAVE_AREA32;\n+\n+#pragma pack(push, 2)\n+typedef struct _CPU_CONTEXT { /* sizeof = 1232 */\n+ uint64_t P1Home;\n+ uint64_t P2Home;\n+ uint64_t P3Home;\n+ uint64_t P4Home;\n+ uint64_t P5Home;\n+ uint64_t P6Home;\n+ uint32_t ContextFlags;\n+ uint32_t MxCsr;\n+ uint16_t SegCs;\n+ uint16_t SegDs;\n+ uint16_t SegEs;\n+ uint16_t SegFs;\n+ uint16_t SegGs;\n+ uint16_t SegSs;\n+ uint32_t EFlags;\n+ uint64_t Dr0;\n+ uint64_t Dr1;\n+ uint64_t Dr2;\n+ uint64_t Dr3;\n+ uint64_t Dr6;\n+ uint64_t Dr7;\n+ uint64_t Rax;\n+ uint64_t Rcx;\n+ uint64_t Rdx;\n+ uint64_t Rbx;\n+ uint64_t Rsp;\n+ uint64_t Rbp;\n+ uint64_t Rsi;\n+ uint64_t Rdi;\n+ uint64_t R8;\n+ uint64_t R9;\n+ uint64_t R10;\n+ uint64_t R11;\n+ uint64_t R12;\n+ uint64_t R13;\n+ uint64_t R14;\n+ uint64_t R15;\n+ uint64_t Rip;\n+ union {\n+ CPU_XMM_SAVE_AREA32 FltSave;\n+ CPU_XMM_SAVE_AREA32 FloatSave;\n+ struct {\n+ CPU_M128A Header[2];\n+ CPU_M128A Legacy[8];\n+ CPU_M128A Xmm0;\n+ CPU_M128A Xmm1;\n+ CPU_M128A Xmm2;\n+ CPU_M128A Xmm3;\n+ CPU_M128A Xmm4;\n+ CPU_M128A Xmm5;\n+ CPU_M128A Xmm6;\n+ CPU_M128A Xmm7;\n+ CPU_M128A Xmm8;\n+ CPU_M128A Xmm9;\n+ CPU_M128A Xmm10;\n+ CPU_M128A Xmm11;\n+ CPU_M128A Xmm12;\n+ CPU_M128A Xmm13;\n+ CPU_M128A Xmm14;\n+ CPU_M128A Xmm15;\n+ };\n+ };\n+ CPU_M128A VectorRegister[26];\n+ uint64_t VectorControl;\n+ uint64_t DebugControl;\n+ uint64_t LastBranchToRip;\n+ uint64_t LastBranchFromRip;\n+ uint64_t LastExceptionToRip;\n+ uint64_t LastExceptionFromRip;\n+} CPU_CONTEXT, *PCPU_CONTEXT;\n+#pragma pack(pop)\n+\n+#else\n+\n+#define SIZE_OF_X86_REG 80\n+#define MAX_SUP_EXT 512\n+\n+#define CPU_CONTEXT_i386 0x10000\n+\n+#define CPU_CONTEXT_CONTROL (CPU_CONTEXT_i386 | 0x1)\n+#define CPU_CONTEXT_INTEGER (CPU_CONTEXT_i386 | 0x2)\n+#define CPU_CONTEXT_SEGMENTS (CPU_CONTEXT_i386 | 0x4)\n+#define CPU_CONTEXT_FLOATING_POINT (CPU_CONTEXT_i386 | 0x8)\n+#define CPU_CONTEXT_DEBUG_REGISTERS (CPU_CONTEXT_i386 | 0x10)\n+#define CPU_CONTEXT_EXTENDED_REGISTERS (CPU_CONTEXT_i386 | 0x20)\n+\n+#define CPU_CONTEXT_FULL \\\n+ (CPU_CONTEXT_CONTROL | CPU_CONTEXT_INTEGER | CPU_CONTEXT_SEGMENTS)\n+#define CPU_CONTEXT_ALL \\\n+ (CPU_CONTEXT_FULL | CPU_CONTEXT_FLOATING_POINT | \\\n+ CPU_CONTEXT_DEBUG_REGISTERS | CPU_CONTEXT_EXTENDED_REGISTERS)\n+\n+typedef struct _CPU_DESCRIPTOR {\n+ uint16_t Pad;\n+ uint16_t Limit;\n+ uint32_t Base;\n+} CPU_DESCRIPTOR, *PCPU_DESCRIPTOR;\n+\n+typedef struct _CPU_KSPECIAL_REGISTERS {\n+ uint32_t Cr0;\n+ uint32_t Cr2;\n+ uint32_t Cr3;\n+ uint32_t Cr4;\n+ uint32_t KernelDr0;\n+ uint32_t KernelDr1;\n+ uint32_t KernelDr2;\n+ uint32_t KernelDr3;\n+ uint32_t KernelDr6;\n+ uint32_t KernelDr7;\n+ CPU_DESCRIPTOR Gdtr;\n+ CPU_DESCRIPTOR Idtr;\n+ uint16_t Tr;\n+ uint16_t Ldtr;\n+ uint32_t Reserved[6];\n+} CPU_KSPECIAL_REGISTERS, *PCPU_KSPECIAL_REGISTERS;\n+\n+typedef struct _CPU_FLOATING_SAVE_AREA {\n+ uint32_t ControlWord;\n+ uint32_t StatusWord;\n+ uint32_t TagWord;\n+ uint32_t ErrorOffset;\n+ uint32_t ErrorSelector;\n+ uint32_t DataOffset;\n+ uint32_t DataSelector;\n+ uint8_t RegisterArea[SIZE_OF_X86_REG];\n+ uint32_t Cr0NpxState;\n+} CPU_FLOATING_SAVE_AREA, *PCPU_FLOATING_SAVE_AREA;\n+\n+typedef struct _CPU_CONTEXT { /* sizeof = 716 */\n+ uint32_t ContextFlags;\n+ uint32_t Dr0;\n+ uint32_t Dr1;\n+ uint32_t Dr2;\n+ uint32_t Dr3;\n+ uint32_t Dr6;\n+ uint32_t Dr7;\n+ CPU_FLOATING_SAVE_AREA FloatSave;\n+ uint32_t SegGs;\n+ uint32_t SegFs;\n+ uint32_t SegEs;\n+ uint32_t SegDs;\n+\n+ uint32_t Edi;\n+ uint32_t Esi;\n+ uint32_t Ebx;\n+ uint32_t Edx;\n+ uint32_t Ecx;\n+ uint32_t Eax;\n+ uint32_t Ebp;\n+ uint32_t Eip;\n+ uint32_t SegCs;\n+ uint32_t EFlags;\n+ uint32_t Esp;\n+ uint32_t SegSs;\n+ uint8_t ExtendedRegisters[MAX_SUP_EXT];\n+} CPU_CONTEXT, *PCPU_CONTEXT;\n+\n+typedef struct _CPU_KPROCESSOR_STATE {\n+ CPU_CONTEXT ContextFrame;\n+ CPU_KSPECIAL_REGISTERS SpecialRegisters;\n+} CPU_KPROCESSOR_STATE, *PCPU_KPROCESSOR_STATE;\n+\n+#endif\n+\n typedef struct KDData {\n InitedAddr KPCR;\n InitedAddr version;\n","prefixes":["23/43"]}