{"id":818515,"url":"http://patchwork.ozlabs.org/api/patches/818515/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20170926103751.21907-5-krebbel@linux.vnet.ibm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170926103751.21907-5-krebbel@linux.vnet.ibm.com>","list_archive_url":null,"date":"2017-09-26T10:37:47","name":"[4/8] S/390: Add FP vec_pack/unpack","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1925df6dee1c8f4fe09509603cf232cb42603d52","submitter":{"id":4421,"url":"http://patchwork.ozlabs.org/api/people/4421/?format=json","name":"Andreas Krebbel","email":"krebbel@linux.vnet.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20170926103751.21907-5-krebbel@linux.vnet.ibm.com/mbox/","series":[{"id":5096,"url":"http://patchwork.ozlabs.org/api/series/5096/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=5096","date":"2017-09-26T10:37:43","name":"S/390: Enable vect tests on S/390 + fixes and improvements","version":1,"mbox":"http://patchwork.ozlabs.org/series/5096/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/818515/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/818515/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-462948-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"lXqO+6QS\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y1crC11gfz9t6C\n\tfor ;\n\tTue, 26 Sep 2017 20:38:50 +1000 (AEST)","(qmail 102514 invoked by alias); 26 Sep 2017 10:38:07 -0000","(qmail 102434 invoked by uid 89); 26 Sep 2017 10:38:07 -0000","from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com)\n\t(148.163.156.1) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tTue, 26 Sep 2017 10:38:05 +0000","from pps.filterd (m0098394.ppops.net [127.0.0.1])\tby\n\tmx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8QAbcfY113921\tfor ;\n\tTue, 26 Sep 2017 06:38:00 -0400","from e06smtp12.uk.ibm.com (e06smtp12.uk.ibm.com\n\t[195.75.94.108])\tby mx0a-001b2d01.pphosted.com with ESMTP id\n\t2d7k4h8g82-1\t(version=TLSv1.2 cipher=AES256-SHA bits=256\n\tverify=NOT)\tfor ;\n\tTue, 26 Sep 2017 06:38:00 -0400","from localhost\tby e06smtp12.uk.ibm.com with IBM ESMTP SMTP\n\tGateway: Authorized Use Only! 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a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:from\n\t:to:subject:date:in-reply-to:references:message-id; s=default;\n\tbh=JNsKQaykdfkoajl0TMgKGzLOcpM=; b=lXqO+6QSQsdU4Dw6wUC/kUvJo6FI\n\tBqH5xGP7mrX+eS6DOLWdINY9EdMiWmByAyPuf3yOuig0eGa3hssShb9Y8QY7rxoE\n\t0dzX2uxsbp7X9c1KbtrJHfEYGOQTtjgluk3z9trGYRDZkypmz4bsBS+GXYFt25jA\n\tuOitf/jp8QVvhz8=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-24.6 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tKAM_LAZY_DOMAIN_SECURITY,\n\tRCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy=","X-HELO":"mx0a-001b2d01.pphosted.com","From":"Andreas Krebbel ","To":"gcc-patches@gcc.gnu.org","Subject":"[PATCH 4/8] S/390: Add FP vec_pack/unpack","Date":"Tue, 26 Sep 2017 12:37:47 +0200","In-Reply-To":"<20170926103751.21907-1-krebbel@linux.vnet.ibm.com>","References":"<20170926103751.21907-1-krebbel@linux.vnet.ibm.com>","X-TM-AS-GCONF":"00","x-cbid":"17092610-0008-0000-0000-0000049A254E","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17092610-0009-0000-0000-00001E2B6F31","Message-Id":"<20170926103751.21907-5-krebbel@linux.vnet.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-26_03:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1 malwarescore=0 phishscore=0\n\tadultscore=1 bulkscore=0 classifier=spam adjust=0 reason=mlx\n\tscancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1709260158","X-IsSubscribed":"yes"},"content":"gcc/ChangeLog:\n\n2017-09-26 Andreas Krebbel \n\n\t* config/s390/vector.md (\"vec_unpacks_lo_v4sf\")\n\t(\"vec_unpacks_hi_v4sf\", \"vec_unpacks_lo_v2df\")\n\t(\"vec_unpacks_hi_v2df\", \"vec_pack_trunc_v2df\"): New expanders.\n---\n gcc/ChangeLog | 6 +++\n gcc/config/s390/vector.md | 96 ++++++++++++++++++++++++++++++++++++++++++++++-\n 2 files changed, 101 insertions(+), 1 deletion(-)","diff":"diff --git a/gcc/ChangeLog b/gcc/ChangeLog\nindex 7843857..d2808b5 100644\n--- a/gcc/ChangeLog\n+++ b/gcc/ChangeLog\n@@ -1,5 +1,11 @@\n 2017-09-26 Andreas Krebbel \n \n+\t* config/s390/vector.md (\"vec_unpacks_lo_v4sf\")\n+\t(\"vec_unpacks_hi_v4sf\", \"vec_unpacks_lo_v2df\")\n+\t(\"vec_unpacks_hi_v2df\", \"vec_pack_trunc_v2df\"): New expanders.\n+\n+2017-09-26 Andreas Krebbel \n+\n \t* config/s390/predicates.md (\"const_shift_by_byte_operand\"): New\n \tpredicate.\n \t* config/s390/vector.md (\"*vec_srb\"): Change modes to V_128\ndiff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md\nindex e61bb88..c15d81d 100644\n--- a/gcc/config/s390/vector.md\n+++ b/gcc/config/s390/vector.md\n@@ -1781,7 +1781,7 @@\n \n ;; vector load lengthened\n \n-; vflls\n+; vflls float -> double\n (define_insn \"*vec_extendv4sf\"\n [(set (match_operand:V2DF 0 \"register_operand\" \"=v\")\n \t(float_extend:V2DF\n@@ -1792,6 +1792,34 @@\n \"vldeb\\t%v0,%v1\"\n [(set_attr \"op_type\" \"VRR\")])\n \n+(define_expand \"vec_unpacks_lo_v4sf\"\n+ [(set (match_dup 2)\n+\t(unspec:V4SF [(match_operand:V4SF 1 \"register_operand\" \"v\")\n+\t\t (match_dup 1)]\n+\t\t UNSPEC_VEC_MERGEL))\n+ (set (match_operand:V2DF 0 \"register_operand\" \"=v\")\n+\t(float_extend:V2DF\n+\t (vec_select:V2SF\n+\t (match_dup 2)\n+\t (parallel [(const_int 0) (const_int 2)]))))]\n+ \"TARGET_VX\"\n+{ operands[2] = gen_reg_rtx(V4SFmode); })\n+\n+(define_expand \"vec_unpacks_hi_v4sf\"\n+ [(set (match_dup 2)\n+\t(unspec:V4SF [(match_operand:V4SF 1 \"register_operand\" \"v\")\n+\t\t (match_dup 1)]\n+\t\t UNSPEC_VEC_MERGEH))\n+ (set (match_operand:V2DF 0 \"register_operand\" \"=v\")\n+\t(float_extend:V2DF\n+\t (vec_select:V2SF\n+\t (match_dup 2)\n+\t (parallel [(const_int 0) (const_int 2)]))))]\n+ \"TARGET_VX\"\n+{ operands[2] = gen_reg_rtx(V4SFmode); })\n+\n+\n+; double -> long double\n (define_insn \"*vec_extendv2df\"\n [(set (match_operand:V1TF 0 \"register_operand\" \"=v\")\n \t(float_extend:V1TF\n@@ -1802,6 +1830,72 @@\n \"wflld\\t%v0,%v1\"\n [(set_attr \"op_type\" \"VRR\")])\n \n+(define_expand \"vec_unpacks_lo_v2df\"\n+ [(set (match_dup 2)\n+\t(unspec:V2DF [(match_operand:V2DF 1 \"register_operand\" \"v\")\n+\t\t (match_dup 1)]\n+\t\t UNSPEC_VEC_MERGEL))\n+ (set (match_operand:V1TF 0 \"register_operand\" \"=v\")\n+\t(float_extend:V1TF\n+\t (vec_select:V1DF\n+\t (match_dup 2)\n+\t (parallel [(const_int 0)]))))]\n+ \"TARGET_VXE\"\n+{ operands[2] = gen_reg_rtx (V2DFmode); })\n+\n+(define_expand \"vec_unpacks_hi_v2df\"\n+ [(set (match_dup 2)\n+\t(unspec:V2DF [(match_operand:V2DF 1 \"register_operand\" \"v\")\n+\t\t (match_dup 1)]\n+\t\t UNSPEC_VEC_MERGEH))\n+ (set (match_operand:V1TF 0 \"register_operand\" \"=v\")\n+\t(float_extend:V1TF\n+\t (vec_select:V1DF\n+\t (match_dup 2)\n+\t (parallel [(const_int 0)]))))]\n+ \"TARGET_VXE\"\n+{ operands[2] = gen_reg_rtx (V2DFmode); })\n+\n+\n+; 2 x v2df -> 1 x v4sf\n+(define_expand \"vec_pack_trunc_v2df\"\n+ [(set (match_dup 3)\n+\t(unspec:V4SF [(match_operand:V2DF 1 \"register_operand\" \"\")\n+\t\t (const_int VEC_INEXACT)\n+\t\t (const_int VEC_RND_CURRENT)]\n+\t\t UNSPEC_VEC_VFLR))\n+ (set (match_dup 4)\n+\t(unspec:V4SF [(match_operand:V2DF 2 \"register_operand\" \"\")\n+\t\t (const_int VEC_INEXACT)\n+\t\t (const_int VEC_RND_CURRENT)]\n+\t\t UNSPEC_VEC_VFLR))\n+ (set (match_dup 6)\n+\t(unspec:V16QI [(subreg:V16QI (match_dup 3) 0)\n+\t\t (subreg:V16QI (match_dup 4) 0)\n+\t\t (match_dup 5)]\n+\t\t UNSPEC_VEC_PERM))\n+ (set (match_operand:V4SF 0 \"register_operand\" \"\")\n+\t(subreg:V4SF (match_dup 6) 0))]\n+ \"TARGET_VX\"\n+{\n+ rtx constv, perm[16];\n+ int i;\n+\n+ for (i = 0; i < 4; ++i)\n+ {\n+ perm[i] = GEN_INT (i);\n+ perm[i + 4] = GEN_INT (i + 8);\n+ perm[i + 8] = GEN_INT (i + 16);\n+ perm[i + 12] = GEN_INT (i + 24);\n+ }\n+ constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));\n+\n+ operands[3] = gen_reg_rtx (V4SFmode);\n+ operands[4] = gen_reg_rtx (V4SFmode);\n+ operands[5] = force_reg (V16QImode, constv);\n+ operands[6] = gen_reg_rtx (V16QImode);\n+})\n+\n ; reduc_smin\n ; reduc_smax\n ; reduc_umin\n","prefixes":["4/8"]}