{"id":818442,"url":"http://patchwork.ozlabs.org/api/patches/818442/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170926041700.22663-2-kalyan.kinthada@alliedtelesis.co.nz/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170926041700.22663-2-kalyan.kinthada@alliedtelesis.co.nz>","list_archive_url":null,"date":"2017-09-26T04:16:59","name":"[1/2] dt-bindings: mtd: pxa3xx: Add \"marvell, nand-force-csx\" compatible string","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":true,"hash":"6bb436f7de8d47c252a04f76c1a2dcea1cea78f4","submitter":{"id":72417,"url":"http://patchwork.ozlabs.org/api/people/72417/?format=json","name":"Kalyan Kinthada","email":"kalyan.kinthada@alliedtelesis.co.nz"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170926041700.22663-2-kalyan.kinthada@alliedtelesis.co.nz/mbox/","series":[{"id":5053,"url":"http://patchwork.ozlabs.org/api/series/5053/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=5053","date":"2017-09-26T04:16:59","name":"Implement guideline when NAND, NOR arbitration is enabled","version":1,"mbox":"http://patchwork.ozlabs.org/series/5053/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/818442/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/818442/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=alliedtelesis.co.nz\n\theader.i=@alliedtelesis.co.nz\n\theader.b=\"faXmPVvq\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1SMm2PJxz9t3x\n\tfor ;\n\tTue, 26 Sep 2017 14:17:08 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S964968AbdIZERG (ORCPT );\n\tTue, 26 Sep 2017 00:17:06 -0400","from gate2.alliedtelesis.co.nz ([202.36.163.20]:47809 \"EHLO\n\tgate2.alliedtelesis.co.nz\" rhost-flags-OK-OK-OK-OK) by\n\tvger.kernel.org with ESMTP id S935992AbdIZERF (ORCPT\n\t); Tue, 26 Sep 2017 00:17:05 -0400","from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (Client did not present a certificate)\n\tby gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id DEAED8365F;\n\tTue, 26 Sep 2017 17:17:02 +1300 (NZDT)","from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with\n\tTrustwave SEG (v7, 5, 8, 10121)\n\tid ; Tue, 26 Sep 2017 17:17:03 +1300","from kalyank-dl.ws.atlnz.lc (kalyank-dl.ws.atlnz.lc [10.33.14.14])\n\tby smtp (Postfix) with ESMTP id 0B88D13EFE5;\n\tTue, 26 Sep 2017 17:17:14 +1300 (NZDT)","by kalyank-dl.ws.atlnz.lc (Postfix, from userid 1628)\n\tid 987DDC07AF; Tue, 26 Sep 2017 17:17:02 +1300 (NZDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; \n\ts=mail; t=1506399422;\n\tbh=Vdag2LsQNnLAbAjzCU0jl423HQl34+6ib2D8vCe1O1c=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References;\n\tb=faXmPVvqpTPHOFJK7NB799WNOxtps/dnwhaMFhUnRLrKkFrtWtpLx0axRks8LV4S/\n\tuVmrLXsBvRvrGiibumqJpN7uCxIe1+jUsJz9MIO0EKHD+KBTQSK2SuPuxiGCCE/eey\n\tCe4b3mFYcaeSIFKdlbuBwWkNHkOAyxJwhU/nTwNA=","From":"Kalyan Kinthada ","To":"dwmw2@infradead.org, computersforpeace@gmail.com,\n\tboris.brezillon@free-electrons.com, marek.vasut@gmail.com,\n\trichard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org,\n\tmark.rutland@arm.com, ezequiel.garcia@free-electrons.com,\n\tdevicetree@vger.kernel.org","Cc":"linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tchris.packham@alliedtelesis.co.nz,\n\tKalyan Kinthada ","Subject":"[PATCH 1/2] dt-bindings: mtd: pxa3xx: Add \"marvell,\n\tnand-force-csx\" compatible string","Date":"Tue, 26 Sep 2017 17:16:59 +1300","Message-Id":"<20170926041700.22663-2-kalyan.kinthada@alliedtelesis.co.nz>","X-Mailer":"git-send-email 2.14.1","In-Reply-To":"<20170926041700.22663-1-kalyan.kinthada@alliedtelesis.co.nz>","References":"<20170926041700.22663-1-kalyan.kinthada@alliedtelesis.co.nz>","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"When the arbitration between NOR and NAND flash is enabled\nthe field bit[21] in the Data Flash Control Register\nneeds to be set to 1 according to guidleine GL-5830741.\n\nThis patch introduces a new compatible string \"marvell,nand-force-csx\"\nwhich is activated through device tree to implement the guideline\nGL-5830741.\n\nSigned-off-by: Kalyan Kinthada \n---\n Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt | 1 +\n 1 file changed, 1 insertion(+)","diff":"diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt\nindex d9b655f11048..157ca7efa3d3 100644\n--- a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt\n+++ b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt\n@@ -20,6 +20,7 @@ Optional properties:\n \t\t\t\tnot present false\n - nand-ecc-strength: number of bits to correct per ECC step\n - nand-ecc-step-size: number of data bytes covered by a single ECC step\n+ - marvell,nand-force-csx: Set to implement guideline when arbitration of NAND and NOR flash is enabled.\n \n The following ECC strength and step size are currently supported:\n \n","prefixes":["1/2"]}