{"id":818383,"url":"http://patchwork.ozlabs.org/api/patches/818383/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com>","list_archive_url":null,"date":"2017-09-25T23:22:04","name":"[v1,3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":true,"hash":"9b1ca05f9b9fa53dbb904f4d711a8a0767e0fc44","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/?format=json","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com/mbox/","series":[{"id":5030,"url":"http://patchwork.ozlabs.org/api/series/5030/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=5030","date":"2017-09-25T23:22:04","name":"NVIDIA Tegra AHB DMA controller driver","version":1,"mbox":"http://patchwork.ozlabs.org/series/5030/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/818383/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/818383/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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The cell represents DMA request select value\n+\t\tfor the peripheral. For more details consult the Tegra TRM's\n+\t\tdocumentation, in particular AHB DMA channel control register\n+\t\tREQ_SEL field.\n+\n+Example:\n+\n+ahbdma: ahbdma@60008000 {\n+\tcompatible = \"nvidia,tegra20-ahbdma\";\n+\treg = <0x60008000 0x2000>;\n+\tinterrupts = ;\n+\tclocks = <&tegra_car TEGRA20_CLK_AHBDMA>;\n+\tresets = <&tegra_car 33>;\n+\t#dma-cells = <1>;\n+};\n","prefixes":["v1","3/5"]}