{"id":818277,"url":"http://patchwork.ozlabs.org/api/patches/818277/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/patch/20170925145352.13145-3-miquel.raynal@free-electrons.com/","project":{"id":3,"url":"http://patchwork.ozlabs.org/api/projects/3/?format=json","name":"Linux MTD development","link_name":"linux-mtd","list_id":"linux-mtd.lists.infradead.org","list_email":"linux-mtd@lists.infradead.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170925145352.13145-3-miquel.raynal@free-electrons.com>","list_archive_url":null,"date":"2017-09-25T14:53:51","name":"[2/3] mtd: nand: pxa3xx: enable NAND controller if the SoC needs it","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"706db5abf535338a6616e8b46684fe67c8f2cc8d","submitter":{"id":71917,"url":"http://patchwork.ozlabs.org/api/people/71917/?format=json","name":"Miquel Raynal","email":"miquel.raynal@free-electrons.com"},"delegate":{"id":58324,"url":"http://patchwork.ozlabs.org/api/users/58324/?format=json","username":"bbrezillon","first_name":"Boris","last_name":"Brezillon","email":"boris.brezillon@free-electrons.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-mtd/patch/20170925145352.13145-3-miquel.raynal@free-electrons.com/mbox/","series":[{"id":4976,"url":"http://patchwork.ozlabs.org/api/series/4976/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-mtd/list/?series=4976","date":"2017-09-25T14:53:50","name":"Enable NAND on Armada-7040-DB board","version":1,"mbox":"http://patchwork.ozlabs.org/series/4976/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/818277/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/818277/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"Marvell recent SoCs like A7k/A8k do not boot with NAND flash\ncontroller activated by default. Enabling the controller is a matter of\nwriting in a system controller register that may also be used for other\nNAND related choices.\n\nThis change is needed to stay bootloader independent.\n\nSigned-off-by: Miquel Raynal \n---\n drivers/mtd/nand/pxa3xx_nand.c | 41 +++++++++++++++++++++++++++++++++++++----\n 1 file changed, 37 insertions(+), 4 deletions(-)","diff":"diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c\nindex 85cff68643e0..90b9a9ccbe60 100644\n--- a/drivers/mtd/nand/pxa3xx_nand.c\n+++ b/drivers/mtd/nand/pxa3xx_nand.c\n@@ -30,6 +30,8 @@\n #include \n #include \n #include \n+#include \n+#include \n \n #define\tCHIP_DELAY_TIMEOUT\tmsecs_to_jiffies(200)\n #define NAND_STOP_DELAY\t\tmsecs_to_jiffies(40)\n@@ -45,6 +47,10 @@\n */\n #define INIT_BUFFER_SIZE\t2048\n \n+/* System control register and bit to enable NAND on some SoCs */\n+#define GENCONF_SOC_DEVICE_MUX\t0x208\n+#define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)\n+\n /* registers and bit definitions */\n #define NDCR\t\t(0x00) /* Control register */\n #define NDTR0CS0\t(0x04) /* Timing Parameter 0 for CS0 */\n@@ -174,6 +180,7 @@ enum {\n enum pxa3xx_nand_variant {\n \tPXA3XX_NAND_VARIANT_PXA,\n \tPXA3XX_NAND_VARIANT_ARMADA370,\n+\tPXA3XX_NAND_VARIANT_ARMADA_8K,\n };\n \n struct pxa3xx_nand_host {\n@@ -425,6 +432,10 @@ static const struct of_device_id pxa3xx_nand_dt_ids[] = {\n \t\t.compatible = \"marvell,armada370-nand\",\n \t\t.data = (void *)PXA3XX_NAND_VARIANT_ARMADA370,\n \t},\n+\t{\n+\t\t.compatible = \"marvell,armada-8k-nand\",\n+\t\t.data = (void *)PXA3XX_NAND_VARIANT_ARMADA_8K,\n+\t},\n \t{}\n };\n MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);\n@@ -825,7 +836,8 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)\n \t\tinfo->retcode = ERR_UNCORERR;\n \tif (status & NDSR_CORERR) {\n \t\tinfo->retcode = ERR_CORERR;\n-\t\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&\n+\t\tif ((info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||\n+\t\t info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) &&\n \t\t info->ecc_bch)\n \t\t\tinfo->ecc_err_cnt = NDSR_ERR_CNT(status);\n \t\telse\n@@ -888,7 +900,8 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)\n \t\tnand_writel(info, NDCB0, info->ndcb2);\n \n \t\t/* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */\n-\t\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n+\t\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||\n+\t\t info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)\n \t\t\tnand_writel(info, NDCB0, info->ndcb3);\n \t}\n \n@@ -1671,7 +1684,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)\n \t\tchip->options |= NAND_BUSWIDTH_16;\n \n \t/* Device detection must be done with ECC disabled */\n-\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n+\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||\n+\t info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)\n \t\tnand_writel(info, NDECCCTRL, 0x0);\n \n \tif (pdata->flash_bbt)\n@@ -1709,7 +1723,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)\n \t * (aka splitted) command handling,\n \t */\n \tif (mtd->writesize > PAGE_CHUNK_SIZE) {\n-\t\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {\n+\t\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||\n+\t\t info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) {\n \t\t\tchip->cmdfunc = nand_cmdfunc_extended;\n \t\t} else {\n \t\t\tdev_err(&info->pdev->dev,\n@@ -1928,6 +1943,24 @@ static int pxa3xx_nand_probe_dt(struct platform_device *pdev)\n \tif (!of_id)\n \t\treturn 0;\n \n+\t/*\n+\t * Some SoCs like A7k/A8k need to enable manually the NAND\n+\t * controller to avoid being bootloader dependent. This is done\n+\t * through the use of a single bit in the System Functions registers.\n+\t */\n+\tif (pxa3xx_nand_get_variant(pdev) == PXA3XX_NAND_VARIANT_ARMADA_8K) {\n+\t\tstruct regmap *sysctrl_base = syscon_regmap_lookup_by_phandle(\n+\t\t\tpdev->dev.of_node, \"marvell,system-controller\");\n+\t\tu32 reg;\n+\n+\t\tif (IS_ERR(sysctrl_base))\n+\t\t\treturn PTR_ERR(sysctrl_base);\n+\n+\t\tregmap_read(sysctrl_base, GENCONF_SOC_DEVICE_MUX, ®);\n+\t\treg |= GENCONF_SOC_DEVICE_MUX_NFC_EN;\n+\t\tregmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg);\n+\t}\n+\n \tpdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);\n \tif (!pdata)\n \t\treturn -ENOMEM;\n","prefixes":["2/3"]}