{"id":818131,"url":"http://patchwork.ozlabs.org/api/patches/818131/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-10-git-send-email-tien.fong.chee@intel.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:05","name":"[U-Boot,v2,09/19] arm: socfpga: Add drivers for programing FPGA from flash","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"a0e9166939ca74a6ab70661b5e91ce3d120053d3","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/?format=json","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-10-git-send-email-tien.fong.chee@intel.com/mbox/","series":[{"id":4901,"url":"http://patchwork.ozlabs.org/api/series/4901/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4901","date":"2017-09-25T08:39:56","name":"Add FPGA, SDRAM, SPL loads U-boot & booting to console","version":2,"mbox":"http://patchwork.ozlabs.org/series/4901/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/818131/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/818131/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0yp14sQhz9tXD\n\tfor ;\n\tMon, 25 Sep 2017 19:04:41 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 6B4C9C220E6; Mon, 25 Sep 2017 08:46:18 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id B330CC22128;\n\tMon, 25 Sep 2017 08:42:14 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 4F900C21DB5; Mon, 25 Sep 2017 08:40:49 +0000 (UTC)","from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 42A49C21F51\n\tfor ; Mon, 25 Sep 2017 08:40:42 +0000 (UTC)","from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Sep 2017 01:40:41 -0700","from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.95])\n\tby fmsmga005.fm.intel.com with ESMTP; 25 Sep 2017 01:40:39 -0700"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,435,1500966000\"; d=\"scan'208\";a=\"155080140\"","From":"tien.fong.chee@intel.com","To":"u-boot@lists.denx.de","Date":"Mon, 25 Sep 2017 16:40:05 +0800","Message-Id":"<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>","Cc":"Marek Vasut , Tien Fong Chee , \n\tChing Liang See ,\n\tTien Fong , \n\tWestergteen Dalon ","Subject":"[U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing\n\tFPGA from flash","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Tien Fong Chee \n\nThese drivers handle FPGA program operation from flash loading\nRBF to memory and then to program FPGA.\n\nSigned-off-by: Tien Fong Chee \n---\n .../include/mach/fpga_manager_arria10.h | 27 ++\n drivers/fpga/socfpga_arria10.c | 391 ++++++++++++++++++++-\n include/altera.h | 6 +\n include/configs/socfpga_common.h | 4 +\n 4 files changed, 425 insertions(+), 3 deletions(-)","diff":"diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h\nindex 9cbf696..93a9122 100644\n--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h\n+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h\n@@ -8,6 +8,8 @@\n #ifndef _FPGA_MANAGER_ARRIA10_H_\n #define _FPGA_MANAGER_ARRIA10_H_\n \n+#include \n+\n #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK\t\tBIT(0)\n #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK\tBIT(1)\n #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK \t\tBIT(2)\n@@ -89,11 +91,36 @@ struct socfpga_fpga_manager {\n \tu32 imgcfg_fifo_status;\n };\n \n+#if defined(CONFIG_CMD_FPGA_LOADFS)\n+enum rbf_type {unknown, periph_section, core_section};\n+enum rbf_security {invalid, unencrypted, encrypted};\n+\n+struct rbf_info {\n+\tenum rbf_type section;\n+\tenum rbf_security security;\n+};\n+\n+struct flash_info {\n+\tchar *interface;\n+\tchar *dev_part;\n+\tchar *filename;\n+\tint fstype;\n+\tu32 remaining;\n+\tu32 flash_offset;\n+\tstruct rbf_info rbfinfo;\n+\tstruct image_header header;\n+};\n+#endif\n+\n /* Functions */\n int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);\n int fpgamgr_program_finish(void);\n int is_fpgamgr_user_mode(void);\n int fpgamgr_wait_early_user_mode(void);\n+#if defined(CONFIG_CMD_FPGA_LOADFS)\n+const char *get_cff_filename(const void *fdt, int *len, u32 core);\n+const char *get_cff_devpart(const void *fdt, int *len);\n+#endif\n \n #endif /* __ASSEMBLY__ */\n \ndiff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c\nindex 5c1a68a..5fe57ef 100644\n--- a/drivers/fpga/socfpga_arria10.c\n+++ b/drivers/fpga/socfpga_arria10.c\n@@ -13,6 +13,12 @@\n #include \n #include \n #include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n #include \n #include \n \n@@ -22,6 +28,10 @@\n #define COMPRESSION_OFFSET\t229\n #define FPGA_TIMEOUT_MSEC\t1000 /* timeout in ms */\n #define FPGA_TIMEOUT_CNT\t0x1000000\n+#define RBF_UNENCRYPTED\t\t0xa65c\n+#define RBF_ENCRYPTED\t\t0xa65d\n+#define ARRIA10RBF_PERIPH\t0x0001\n+#define ARRIA10RBF_CORE\t\t0x8001\n \n DECLARE_GLOBAL_DATA_PTR;\n \n@@ -112,13 +122,14 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void)\n \tunsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |\n \t\t\t\tALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;\n \n-\t/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,\n-\t * timeout at 1000ms\n+\t/*\n+\t * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until\n+\t * de-asserted, timeout at 1000ms\n \t */\n \treturn wait_for_bit(__func__,\n \t\t\t &fpga_manager_base->imgcfg_stat,\n \t\t\t mask,\n-\t\t\t false, FPGA_TIMEOUT_MSEC, false);\n+\t\t\t true, FPGA_TIMEOUT_MSEC, false);\n }\n \n static int wait_for_f2s_nstatus_pin(unsigned long value)\n@@ -469,6 +480,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)\n \n \t/* Initialize the FPGA Manager */\n \tstatus = fpgamgr_program_init((u32 *)rbf_data, rbf_size);\n+\n \tif (status)\n \t\treturn status;\n \n@@ -477,3 +489,376 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)\n \n \treturn fpgamgr_program_finish();\n }\n+\n+#if defined(CONFIG_CMD_FPGA_LOADFS)\n+const char *get_cff_filename(const void *fdt, int *len, u32 core)\n+{\n+\tconst char *cff_filename = NULL;\n+\tconst char *cell;\n+\tint nodeoffset;\n+\tnodeoffset = fdtdec_next_compatible(fdt, 0,\n+\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\n+\n+\tif (nodeoffset >= 0) {\n+\t\tif (core)\n+\t\t\tcell = fdt_getprop(fdt,\n+\t\t\t\t\tnodeoffset,\n+\t\t\t\t\t\"bitstream_core\",\n+\t\t\t\t\tlen);\n+\t\telse\n+\t\t\tcell = fdt_getprop(fdt, nodeoffset, \"bitstream_periph\",\n+\t\t\t\t\t len);\n+\n+\t\tif (cell)\n+\t\t\tcff_filename = cell;\n+\t}\n+\n+\treturn cff_filename;\n+}\n+\n+const char *get_cff_devpart(const void *fdt, int *len)\n+{\n+\tconst char *cff_devpart = NULL;\n+\tconst char *cell;\n+\tint nodeoffset;\n+\tnodeoffset = fdtdec_next_compatible(fdt, 0,\n+\t\t\t COMPAT_ALTERA_SOCFPGA_FPGA0);\n+\n+\tcell = fdt_getprop(fdt, nodeoffset, \"bitstream_devpart\", len);\n+\n+\tif (cell)\n+\t\tcff_devpart = cell;\n+\n+\treturn cff_devpart;\n+}\n+\n+void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)\n+{\n+\t/*\n+\t * Magic ID starting at:\n+\t * -> 1st dword in periph.rbf\n+\t * -> 2nd dword in core.rbf\n+\t */\n+\tu32 word_reading_max = 2;\n+\tu32 i;\n+\n+\tfor (i = 0; i < word_reading_max; i++) {\n+\t\tif (RBF_UNENCRYPTED == *(buffer + i)) /* PERIPH RBF */\n+\t\t\trbf->security = unencrypted;\n+\t\telse if (RBF_ENCRYPTED == *(buffer + i))\n+\t\t\t\trbf->security = encrypted;\n+\t\telse if (RBF_UNENCRYPTED == *(buffer + i + 1)) /* CORE RBF */\n+\t\t\t\trbf->security = unencrypted;\n+\t\telse if (RBF_ENCRYPTED == *(buffer + i + 1))\n+\t\t\t\trbf->security = encrypted;\n+\t\telse {\n+\t\t\trbf->security = invalid;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\t/* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */\n+\t\tif (ARRIA10RBF_PERIPH == *(buffer + i + 1)) {\n+\t\t\trbf->section = periph_section;\n+\t\t\tbreak;\n+\t\t} else if (ARRIA10RBF_CORE == *(buffer + i + 1)) {\n+\t\t\trbf->section = core_section;\n+\t\t\tbreak;\n+\t\t} else if (ARRIA10RBF_PERIPH == *(buffer + i + 2)) {\n+\t\t\trbf->section = periph_section;\n+\t\t\tbreak;\n+\t\t} else if (ARRIA10RBF_CORE == *(buffer + i + 2)) {\n+\t\t\trbf->section = core_section;\n+\t\t\tbreak;\n+\t\t} else {\n+\t\t\trbf->section = unknown;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn;\n+}\n+\n+static int flash_read(struct flash_info *flashinfo,\n+\tu32 size_read,\n+\tu32 *buffer_ptr)\n+{\n+\tsize_t ret = EEXIST;\n+\tloff_t actread = 0;\n+\n+\tif (fs_set_blk_dev(flashinfo->interface, flashinfo->dev_part,\n+\t\t\t\tflashinfo->fstype))\n+\t\treturn FPGA_FAIL;\n+\n+\tret = fs_read(flashinfo->filename,\n+\t\t\t(u32) buffer_ptr, flashinfo->flash_offset,\n+\t\t\tsize_read, &actread);\n+\n+\tif (ret || actread != size_read) {\n+\t\tprintf(\"Failed to read %s from flash %d \",\n+\t\t\tflashinfo->filename,\n+\t\t\t ret);\n+\t\tprintf(\"!= %d.\\n\", size_read);\n+\t\treturn -EPERM;\n+\t\t} else\n+\t\t\tret = actread;\n+\n+\treturn ret;\n+}\n+\n+static int fs_flash_preinit(struct flash_info *flashinfo,\n+\tu32 *buffer, u32 *buffer_sizebytes)\n+{\n+\tu32 *bufferptr_after_header = NULL;\n+\tu32 buffersize_after_header = 0;\n+\tu32 rbf_header_data_size = 0;\n+\tint ret = 0;\n+\n+\tflashinfo->flash_offset = 0;\n+\n+\t/* To avoid from keeping re-read the contents */\n+\tstruct image_header *header = &(flashinfo->header);\n+\tsize_t buffer_size = *buffer_sizebytes;\n+\tu32 *buffer_ptr = (u32 *)*buffer;\n+\n+\t /* Load mkimage header into buffer */\n+\tret = flash_read(flashinfo,\n+\t\t\tsizeof(struct image_header), buffer_ptr);\n+\n+\tif (0 >= ret) {\n+\t\tprintf(\" Failed to read mkimage header from flash.\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\n+\tWATCHDOG_RESET();\n+\n+\tmemcpy(header, (u_char *)buffer_ptr, sizeof(*header));\n+\n+\tif (!image_check_magic(header)) {\n+\t\tprintf(\"FPGA: Bad Magic Number.\\n\");\n+\t\treturn -EBADF;\n+\t}\n+\n+\tif (!image_check_hcrc(header)) {\n+\t\tprintf(\"FPGA: Bad Header Checksum.\\n\");\n+\t\treturn -EPERM;\n+\t}\n+\n+\t/* Getting rbf data size */\n+\tflashinfo->remaining =\n+\t\timage_get_data_size(header);\n+\n+\t/* Calculate total size of both rbf data with mkimage header */\n+\trbf_header_data_size = flashinfo->remaining +\n+\t\t\t\tsizeof(struct image_header);\n+\n+\t/* Loading to buffer chunk by chunk, normally for OCRAM buffer */\n+\tif (rbf_header_data_size > buffer_size) {\n+\t\t/* Calculate size of rbf data in the buffer */\n+\t\tbuffersize_after_header =\n+\t\t\tbuffer_size - sizeof(struct image_header);\n+\t\tflashinfo->remaining -= buffersize_after_header;\n+\t} else {\n+\t/* Loading whole rbf image into buffer, normally for DDR buffer */\n+\t\tbuffer_size = rbf_header_data_size;\n+\t\t/* Calculate size of rbf data in the buffer */\n+\t\tbuffersize_after_header =\n+\t\t\tbuffer_size - sizeof(struct image_header);\n+\t\tflashinfo->remaining = 0;\n+\t}\n+\n+\t/* Loading mkimage header and rbf data into buffer */\n+\tret = flash_read(flashinfo, buffer_size, buffer_ptr);\n+\n+\tif (0 >= ret) {\n+\t\tprintf(\" Failed to read mkimage header and rbf data \");\n+\t\tprintf(\"from flash.\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\n+\t/*\n+\t * Getting pointer of rbf data starting address where is it\n+\t * right after mkimage header\n+\t */\n+\tbufferptr_after_header =\n+\t\t(u32 *)((u_char *)buffer_ptr + sizeof(struct image_header));\n+\n+\t/* Update next reading rbf data flash offset */\n+\tflashinfo->flash_offset += buffer_size;\n+\n+\t/*\n+\t * Update the starting addr of rbf data to init FPGA & programming\n+\t * into FPGA\n+\t */\n+\t*buffer = (u32)bufferptr_after_header;\n+\n+\tget_rbf_image_info(&flashinfo->rbfinfo, (u16 *)bufferptr_after_header);\n+\n+\t/* Update the size of rbf data to be programmed into FPGA */\n+\t*buffer_sizebytes = buffersize_after_header;\n+\n+#ifdef CONFIG_CHECK_FPGA_DATA_CRC\n+\tflashinfo->datacrc =\n+\t\tcrc32(flashinfo->datacrc,\n+\t\t(u_char *)bufferptr_after_header,\n+\t\tbuffersize_after_header);\n+#endif\n+\n+if (0 == flashinfo->remaining) {\n+#ifdef CONFIG_CHECK_FPGA_DATA_CRC\n+\tif (flashinfo->datacrc !=\n+\t\timage_get_dcrc(&(flashinfo->header))) {\n+\t\tprintf(\"FPGA: Bad Data Checksum.\\n\");\n+\t\treturn -EPERM;\n+\t}\n+#endif\n+}\n+\treturn 0;\n+}\n+\n+static int fs_flash_read(struct flash_info *flashinfo, u32 *buffer,\n+\tu32 *buffer_sizebytes)\n+{\n+\tint ret = 0;\n+\t/* To avoid from keeping re-read the contents */\n+\tsize_t buffer_size = *buffer_sizebytes;\n+\tu32 *buffer_ptr = (u32 *)*buffer;\n+\tu32 flash_addr = flashinfo->flash_offset;\n+\n+\t/* Buffer allocated in OCRAM */\n+\t/* Read the data by small chunk by chunk. */\n+\tif (flashinfo->remaining > buffer_size)\n+\t\tflashinfo->remaining -= buffer_size;\n+\telse {\n+\t\t/*\n+\t\t * Buffer allocated in DDR, larger than rbf data most\n+\t\t * of the time\n+\t\t */\n+\t\tbuffer_size = flashinfo->remaining;\n+\t\tflashinfo->remaining = 0;\n+\t}\n+\n+\tret = flash_read(flashinfo, buffer_size, buffer_ptr);\n+\n+\tif (0 >= ret) {\n+\t\tprintf(\" Failed to read rbf data from flash.\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\n+#ifdef CONFIG_CHECK_FPGA_DATA_CRC\n+\tflashinfo->datacrc =\n+\t\tcrc32(flashinfo->datacrc,\n+\t\t\t(unsigned char *)buffer_ptr, buffer_size);\n+#endif\n+\n+if (0 == flashinfo->remaining) {\n+#ifdef CONFIG_CHECK_FPGA_DATA_CRC\n+\tif (flashinfo->datacrc !=\n+\t\timage_get_dcrc(&(flashinfo->header))) {\n+\t\tprintf(\"FPGA: Bad Data Checksum.\\n\");\n+\t\treturn -EPERM;\n+\t}\n+#endif\n+}\n+\t/* Update next reading rbf data flash offset */\n+\tflash_addr += buffer_size;\n+\n+\tflashinfo->flash_offset = flash_addr;\n+\n+\t/* Update the size of rbf data to be programmed into FPGA */\n+\t*buffer_sizebytes = buffer_size;\n+\n+\treturn 0;\n+}\n+\n+int socfpga_loadfs(Altera_desc *desc, const void *buf, size_t bsize,\n+\t\t fpga_fs_info *fpga_fsinfo)\n+{\n+\tu32 buffer = 0;\n+\tu32 buffer_ori = 0;\n+\tsize_t buffer_sizebytes = 0;\n+\tsize_t buffer_sizebytes_ori = 0;\n+\tstruct flash_info flashinfo;\n+\tu32 status = 0;\n+\tint ret = 0;\n+\n+\tmemset(&flashinfo, 0, sizeof(flashinfo));\n+\n+\tif (fpga_fsinfo->filename == NULL) {\n+\t\tprintf(\"no peripheral RBF filename specified.\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tWATCHDOG_RESET();\n+\n+\tbuffer_sizebytes = buffer_sizebytes_ori = bsize;\n+\tbuffer = buffer_ori = (u32) buf;\n+\tflashinfo.interface = fpga_fsinfo->interface;\n+\tflashinfo.dev_part = fpga_fsinfo->dev_part;\n+\tflashinfo.filename = fpga_fsinfo->filename;\n+\tflashinfo.fstype = fpga_fsinfo->fstype;\n+\n+\t/*\n+\t * Note: Both buffer and buffer_sizebytes values can be altered by\n+\t * function below.\n+\t */\n+\tret = fs_flash_preinit(&flashinfo, &buffer, &buffer_sizebytes);\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (periph_section == flashinfo.rbfinfo.section) {\n+\t\t/* Initialize the FPGA Manager */\n+\t\tstatus = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);\n+\t\tif (status) {\n+\t\t\tprintf(\"FPGA: Init with periph rbf failed with error. \");\n+\t\t\tprintf(\"code %d\\n\", status);\n+\t\t\treturn -EPERM;\n+\t\t}\n+\t}\n+\n+\tWATCHDOG_RESET();\n+\n+\t/* Transfer data to FPGA Manager */\n+\tfpgamgr_program_write((void *)buffer,\n+\t\tbuffer_sizebytes);\n+\n+\tWATCHDOG_RESET();\n+\n+\twhile (flashinfo.remaining) {\n+\t\tret = fs_flash_read(&flashinfo, &buffer_ori,\n+\t\t\t&buffer_sizebytes_ori);\n+\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\t/* transfer data to FPGA Manager */\n+\t\tfpgamgr_program_write((void *)buffer_ori,\n+\t\t\tbuffer_sizebytes_ori);\n+\n+\t\tWATCHDOG_RESET();\n+\t}\n+\n+\tif (periph_section == flashinfo.rbfinfo.section) {\n+\t\tif (-ETIMEDOUT != fpgamgr_wait_early_user_mode())\n+\t\t\tprintf(\"FPGA: Early Release Succeeded.\\n\");\n+\t\telse {\n+\t\t\tprintf(\"FPGA: Failed to see Early Release.\\n\");\n+\t\t\treturn -EIO;\n+\t\t}\n+\t} else if (core_section == flashinfo.rbfinfo.section) {\n+\t\t/* Ensure the FPGA entering config done */\n+\t\tstatus = fpgamgr_program_finish();\n+\t\tif (status)\n+\t\t\treturn status;\n+\t\telse\n+\t\t\tprintf(\"FPGA: Enter user mode.\\n\");\n+\n+\t} else {\n+\t\tprintf(\"Config Error: Unsupported FGPA raw binary type.\\n\");\n+\t\treturn -ENOEXEC;\n+\t}\n+\n+\tWATCHDOG_RESET();\n+\treturn 1;\n+}\n+#endif\ndiff --git a/include/altera.h b/include/altera.h\nindex 48d3eb7..0597e8a 100644\n--- a/include/altera.h\n+++ b/include/altera.h\n@@ -84,6 +84,10 @@ typedef struct {\n extern int altera_load(Altera_desc *desc, const void *image, size_t size);\n extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize);\n extern int altera_info(Altera_desc *desc);\n+#if defined(CONFIG_CMD_FPGA_LOADFS)\n+int altera_loadfs(Altera_desc *desc, const void *buf, size_t bsize,\n+\t\t fpga_fs_info *fpga_fsinfo);\n+#endif\n \n /* Board specific implementation specific function types\n *********************************************************************/\n@@ -111,6 +115,8 @@ typedef struct {\n \n #ifdef CONFIG_FPGA_SOCFPGA\n int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);\n+int socfpga_loadfs(Altera_desc *desc, const void *buf, size_t bsize,\n+\t\t fpga_fs_info *fpga_fsinfo);\n #endif\n \n #ifdef CONFIG_FPGA_STRATIX_V\ndiff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h\nindex 9897e11..eadce2d 100644\n--- a/include/configs/socfpga_common.h\n+++ b/include/configs/socfpga_common.h\n@@ -27,7 +27,11 @@\n */\n #define CONFIG_NR_DRAM_BANKS\t\t1\n #define PHYS_SDRAM_1\t\t\t0x0\n+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n #define CONFIG_SYS_MALLOC_LEN\t\t(64 * 1024 * 1024)\n+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n+#define CONFIG_SYS_MALLOC_LEN\t\t(128 * 1024 * 1024)\n+#endif\n #define CONFIG_SYS_MEMTEST_START\tPHYS_SDRAM_1\n #define CONFIG_SYS_MEMTEST_END\t\tPHYS_SDRAM_1_SIZE\n #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n","prefixes":["U-Boot","v2","09/19"]}