{"id":818109,"url":"http://patchwork.ozlabs.org/api/patches/818109/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-20-git-send-email-tien.fong.chee@intel.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506328815-23733-20-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:15","name":"[U-Boot,v2,19/19] arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"55d85afb7925181bebccef71ec65912f4ed302c8","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/?format=json","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-20-git-send-email-tien.fong.chee@intel.com/mbox/","series":[{"id":4901,"url":"http://patchwork.ozlabs.org/api/series/4901/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4901","date":"2017-09-25T08:39:56","name":"Add FPGA, SDRAM, SPL loads U-boot & booting to console","version":2,"mbox":"http://patchwork.ozlabs.org/series/4901/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/818109/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/818109/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0yVR05hCz9s76\n\tfor ;\n\tMon, 25 Sep 2017 18:51:10 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 4A439C21F51; Mon, 25 Sep 2017 08:46:51 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id DC686C21FA9;\n\tMon, 25 Sep 2017 08:43:05 +0000 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+0800","Message-Id":"<1506328815-23733-20-git-send-email-tien.fong.chee@intel.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>","Cc":"Marek Vasut , Tien Fong Chee , \n\tChing Liang See ,\n\tTien Fong , \n\tWestergteen Dalon ","Subject":"[U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading U-boot\n\tto DDR and booting U-boot","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Tien Fong Chee \n\nEnable SPL loading U-boot from SDMMC to DDR and booting U-boot.\n\nSigned-off-by: Tien Fong Chee \n---\n arch/arm/mach-socfpga/spl.c | 55 +++++++++++++++++++++++++++++++++++++\n common/spl/spl_mmc.c | 2 +-\n configs/socfpga_arria10_defconfig | 57 ++++++++++++++++++++++++++++++++++-----\n include/spl.h | 2 ++\n 4 files changed, 108 insertions(+), 8 deletions(-)","diff":"diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c\nindex aba116d..9b381bb 100644\n--- a/arch/arm/mach-socfpga/spl.c\n+++ b/arch/arm/mach-socfpga/spl.c\n@@ -15,6 +15,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -22,6 +23,10 @@\n #include \n #include \n #include \n+#include \n+#include \n+#include \n+#include \n #include \n #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n #include \n@@ -29,6 +34,9 @@\n \n DECLARE_GLOBAL_DATA_PTR;\n \n+#define BSIZE\t4096\n+#define PERIPH_RBF\t0\n+\n #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n static struct pl310_regs *const pl310 =\n \t(struct pl310_regs *)CONFIG_SYS_PL310_BASE;\n@@ -197,6 +205,12 @@ void board_init_f(ulong dummy)\n #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n void spl_board_init(void)\n {\n+\tint rval = 0;\n+\tint len = 0;\n+\tu32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);\n+\tstruct spl_boot_device bootdev;\n+\tfpga_fs_info fpga_fsinfo;\n+\n \t/* configuring the clock based on handoff */\n \tcm_basic_init(gd->fdt_blob);\n \tWATCHDOG_RESET();\n@@ -214,6 +228,47 @@ void spl_board_init(void)\n \n \t/* Add device descriptor to FPGA device table */\n \tsocfpga_fpga_add();\n+\n+\tbootdev.boot_device = spl_boot_device();\n+\n+\tif (BOOT_DEVICE_MMC1 == bootdev.boot_device) {\n+\t\tstruct mmc *mmc = NULL;\n+\t\tint err = 0;\n+\n+\t\tspl_mmc_find_device(&mmc, bootdev.boot_device);\n+\n+\t\terr = mmc_init(mmc);\n+\n+\t\tif (err) {\n+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT\n+\t\t\tprintf(\"spl: mmc init failed with error: %d\\n\", err);\n+#endif\n+\t\t}\n+\n+\t\tfpga_fsinfo.dev_part = (char *)get_cff_devpart(gd->fdt_blob,\n+\t\t\t\t\t\t\t\t &len);\n+\n+\t\tfpga_fsinfo.filename = (char *)get_cff_filename(gd->fdt_blob,\n+\t\t\t\t\t\t\t\t &len,\n+\t\t\t\t\t\t\t\tPERIPH_RBF);\n+\n+\t\tfpga_fsinfo.interface = \"mmc\";\n+\n+\t\tfpga_fsinfo.fstype = FS_TYPE_FAT;\n+\t} else {\n+\t\tprintf(\"Invalid boot device!\\n\");\n+\t\treturn;\n+\t}\n+\n+\t/* Program peripheral RBF */\n+\tif (fpga_fsinfo.filename && fpga_fsinfo.dev_part && (len > 0))\n+\t\trval = fpga_fsload(0, buffer, BSIZE, &fpga_fsinfo);\n+\n+\tif (rval > 0) {\n+\t\tconfig_pins(gd->fdt_blob, \"shared\");\n+\n+\t\tddr_calibration_sequence();\n+\t}\n }\n \n void board_init_f(ulong dummy)\ndiff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c\nindex b2cccc6..159443f 100644\n--- a/common/spl/spl_mmc.c\n+++ b/common/spl/spl_mmc.c\n@@ -113,7 +113,7 @@ static int spl_mmc_get_device_index(u32 boot_device)\n \treturn -ENODEV;\n }\n \n-static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)\n+int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)\n {\n #if CONFIG_IS_ENABLED(DM_MMC)\n \tstruct udevice *dev;\ndiff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig\nindex 4c73d73..2ff9801 100644\n--- a/configs/socfpga_arria10_defconfig\n+++ b/configs/socfpga_arria10_defconfig\n@@ -2,33 +2,76 @@ CONFIG_ARM=y\n CONFIG_ARCH_SOCFPGA=y\n CONFIG_SYS_MALLOC_F_LEN=0x2000\n CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y\n+CONFIG_SPL_STACK_R_ADDR=0x00800000\n CONFIG_IDENT_STRING=\"socfpga_arria10\"\n CONFIG_DEFAULT_DEVICE_TREE=\"socfpga_arria10_socdk_sdmmc\"\n-CONFIG_USE_BOOTARGS=y\n-CONFIG_BOOTARGS=\"console=ttyS0,115200\"\n CONFIG_DEFAULT_FDT_FILE=\"socfpga_arria10_socdk_sdmmc.dtb\"\n+CONFIG_FIT=y\n+CONFIG_SYS_CONSOLE_IS_IN_ENV=y\n+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y\n+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y\n+CONFIG_SPL_ENV_SUPPORT=y\n+CONFIG_VERSION_VARIABLE=y\n CONFIG_SPL=y\n+CONFIG_HUSH_PARSER=y\n CONFIG_SPL_FPGA_SUPPORT=y\n+CONFIG_SPL_FAT_SUPPORT=y\n+CONFIG_FS_FAT_MAX_CLUSTSIZE=32768\n CONFIG_CMD_BOOTZ=y\n # CONFIG_CMD_IMLS is not set\n CONFIG_CMD_ASKENV=y\n CONFIG_CMD_GREPENV=y\n # CONFIG_CMD_FLASH is not set\n-CONFIG_CMD_GPIO=y\n+CONFIG_SPL_LIBDISK_SUPPORT=y\n+CONFIG_CMD_PART=y\n CONFIG_CMD_MMC=y\n+CONFIG_CMD_SF=y\n+CONFIG_CMD_SPI=y\n+CONFIG_CMD_I2C=y\n+CONFIG_SYS_I2C_DW=y\n+CONFIG_CMD_USB=y\n+CONFIG_CMD_DFU=y\n+CONFIG_CMD_USB_MASS_STORAGE=y\n+CONFIG_CMD_GPIO=y\n+CONFIG_CMD_MII=y\n CONFIG_CMD_DHCP=y\n CONFIG_CMD_PING=y\n CONFIG_CMD_CACHE=y\n-CONFIG_CMD_EXT4=y\n-CONFIG_CMD_EXT4_WRITE=y\n CONFIG_DOS_PARTITION=y\n-# CONFIG_SPL_DOS_PARTITION is not set\n-CONFIG_ENV_IS_IN_MMC=y\n+CONFIG_SPL_DOS_PARTITION=y\n+CONFIG_SPL_FS_GENERIC=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_FS_GENERIC=y\n CONFIG_SPL_DM=y\n CONFIG_SPL_DM_SEQ_ALIAS=y\n+CONFIG_DFU_MMC=y\n CONFIG_FPGA_SOCFPGA=y\n CONFIG_DM_GPIO=y\n CONFIG_DWAPB_GPIO=y\n CONFIG_DM_MMC=y\n+CONFIG_MMC_DW=y\n+CONFIG_SPI_FLASH=y\n+CONFIG_SPI_FLASH_BAR=y\n+CONFIG_SPI_FLASH_SPANSION=y\n+CONFIG_SPI_FLASH_STMICRO=y\n+CONFIG_DM_ETH=y\n+CONFIG_ETH_DESIGNWARE=y\n CONFIG_SYS_NS16550=y\n CONFIG_USE_TINY_PRINTF=y\n+CONFIG_CMD_FPGA_LOADFS=y\n+CONFIG_CADENCE_QSPI=y\n+CONFIG_DESIGNWARE_SPI=y\n+CONFIG_USB=y\n+CONFIG_DM_USB=y\n+CONFIG_USB_STORAGE=y\n+CONFIG_USB_GADGET=y\n+CONFIG_USB_GADGET_DWC2_OTG=y\n+CONFIG_USB_GADGET_DOWNLOAD=y\n+CONFIG_G_DNL_MANUFACTURER=\"altera\"\n+CONFIG_G_DNL_VENDOR_NUM=0x0525\n+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5\n+CONFIG_USE_TINY_PRINTF=y\n+CONFIG_SPL_MMC_SUPPORT=y\n+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y\n+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800\n+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y\ndiff --git a/include/spl.h b/include/spl.h\nindex ce4cf0a..e24433d 100644\n--- a/include/spl.h\n+++ b/include/spl.h\n@@ -10,6 +10,7 @@\n /* Platform-specific defines */\n #include \n #include \n+#include \n \n /* Value in r0 indicates we booted from U-Boot */\n #define UBOOT_NOT_LOADED_FROM_SPL\t0x13578642\n@@ -68,6 +69,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,\n void preloader_console_init(void);\n u32 spl_boot_device(void);\n u32 spl_boot_mode(const u32 boot_device);\n+int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);\n \n /**\n * spl_set_header_raw_uboot() - Set up a standard SPL image structure\n","prefixes":["U-Boot","v2","19/19"]}