{"id":818107,"url":"http://patchwork.ozlabs.org/api/patches/818107/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-12-git-send-email-tien.fong.chee@intel.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506328815-23733-12-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:07","name":"[U-Boot,v2,11/19] arm: socfpga: Add DRAM bank size initialization function","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"4f1a7e4bab1e44c402cdb42d3326a003e982464a","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/?format=json","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-12-git-send-email-tien.fong.chee@intel.com/mbox/","series":[{"id":4901,"url":"http://patchwork.ozlabs.org/api/series/4901/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4901","date":"2017-09-25T08:39:56","name":"Add FPGA, SDRAM, SPL loads U-boot & booting to console","version":2,"mbox":"http://patchwork.ozlabs.org/series/4901/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/818107/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/818107/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0ySw4yb8z9tXG\n\tfor ;\n\tMon, 25 Sep 2017 18:49:52 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 5C1F0C21DED; Mon, 25 Sep 2017 08:45:46 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 6D7B6C220F1;\n\tMon, 25 Sep 2017 08:41:56 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 5A66FC22025; Mon, 25 Sep 2017 08:40:54 +0000 (UTC)","from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 01EC8C21FFF\n\tfor ; Mon, 25 Sep 2017 08:40:46 +0000 (UTC)","from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Sep 2017 01:40:46 -0700","from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.95])\n\tby fmsmga005.fm.intel.com with ESMTP; 25 Sep 2017 01:40:44 -0700"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,435,1500966000\"; d=\"scan'208\";a=\"155080157\"","From":"tien.fong.chee@intel.com","To":"u-boot@lists.denx.de","Date":"Mon, 25 Sep 2017 16:40:07 +0800","Message-Id":"<1506328815-23733-12-git-send-email-tien.fong.chee@intel.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>","Cc":"Marek Vasut , Tien Fong Chee , \n\tChing Liang See ,\n\tTien Fong , \n\tWestergteen Dalon ","Subject":"[U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size\n\tinitialization function","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Tien Fong Chee \n\nAdd function for both multiple DRAM bank and single DRAM bank size\ninitialization. This common functionality could be used by every single\nSOCFPGA board.\n\nSigned-off-by: Tien Fong Chee \n---\n arch/arm/mach-socfpga/board.c | 7 +++++++\n include/configs/socfpga_common.h | 1 +\n 2 files changed, 8 insertions(+)","diff":"diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c\nindex a41d089..965f9dc 100644\n--- a/arch/arm/mach-socfpga/board.c\n+++ b/arch/arm/mach-socfpga/board.c\n@@ -29,6 +29,13 @@ int board_init(void)\n \treturn 0;\n }\n \n+int dram_init_banksize(void)\n+{\n+\tfdtdec_setup_memory_banksize();\n+\n+\treturn 0;\n+}\n+\n #ifdef CONFIG_USB_GADGET\n struct dwc2_plat_otg_data socfpga_otg_data = {\n \t.usb_gusbcfg\t= 0x1417,\ndiff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h\nindex eadce2d..7549ee8 100644\n--- a/include/configs/socfpga_common.h\n+++ b/include/configs/socfpga_common.h\n@@ -47,6 +47,7 @@\n \t(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)\n \n #define CONFIG_SYS_SDRAM_BASE\t\tPHYS_SDRAM_1\n+#define CONFIG_SYS_SDRAM_SIZE\t\tPHYS_SDRAM_1_SIZE\n #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET\n #define CONFIG_SYS_TEXT_BASE\t\t0x08000040\n #else\n","prefixes":["U-Boot","v2","11/19"]}