{"id":818105,"url":"http://patchwork.ozlabs.org/api/patches/818105/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-6-git-send-email-tien.fong.chee@intel.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506328815-23733-6-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:01","name":"[U-Boot,v2,05/19] arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytes","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"3b891deb945b761754500f708595ab66a25adc27","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/?format=json","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-6-git-send-email-tien.fong.chee@intel.com/mbox/","series":[{"id":4901,"url":"http://patchwork.ozlabs.org/api/series/4901/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4901","date":"2017-09-25T08:39:56","name":"Add FPGA, SDRAM, SPL loads U-boot & booting to console","version":2,"mbox":"http://patchwork.ozlabs.org/series/4901/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/818105/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/818105/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0yN81gMWz9tXG\n\tfor ;\n\tMon, 25 Sep 2017 18:45:44 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid D7DCBC21C8F; Mon, 25 Sep 2017 08:42:02 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 32405C21F51;\n\tMon, 25 Sep 2017 08:40:50 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid B607FC21C26; Mon, 25 Sep 2017 08:40:37 +0000 (UTC)","from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 61B51C21F51\n\tfor ; Mon, 25 Sep 2017 08:40:32 +0000 (UTC)","from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Sep 2017 01:40:32 -0700","from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.95])\n\tby fmsmga005.fm.intel.com with ESMTP; 25 Sep 2017 01:40:30 -0700"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,435,1500966000\"; d=\"scan'208\";a=\"155080102\"","From":"tien.fong.chee@intel.com","To":"u-boot@lists.denx.de","Date":"Mon, 25 Sep 2017 16:40:01 +0800","Message-Id":"<1506328815-23733-6-git-send-email-tien.fong.chee@intel.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>","Cc":"Marek Vasut , Tien Fong Chee , \n\tChing Liang See ,\n\tTien Fong , \n\tWestergteen Dalon ","Subject":"[U-Boot] [PATCH v2 05/19] arm: socfpga: Enhance FPGA program write\n\trbf data with size >= 4 bytes","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Tien Fong Chee \n\nExisting FPGA program write is always assume RBF data >= 32 bytes, so\nany rbf data less than 32 bytes writing to FPGA would be failed.\nThis patch enhances the FPGA program write to support rbf data with\nsize >= 4 bytes.\n\nSigned-off-by: Tien Fong Chee \n---\n drivers/fpga/socfpga.c | 14 ++++++++------\n 1 file changed, 8 insertions(+), 6 deletions(-)","diff":"diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c\nindex 28fa16b..6e14ebd 100644\n--- a/drivers/fpga/socfpga.c\n+++ b/drivers/fpga/socfpga.c\n@@ -1,5 +1,5 @@\n /*\n- * Copyright (C) 2012 Altera Corporation \n+ * Copyright (C) 2012-2017 Altera Corporation \n * All rights reserved.\n *\n * SPDX-License-Identifier:\tBSD-3-Clause\n@@ -55,18 +55,20 @@ void fpgamgr_program_write(const void *rbf_data, size_t rbf_size)\n \tuint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);\n \n \tasm volatile(\n+\t\t\"\tcmp\t%2,\t#0\\n\"\n+\t\t\"\tbeq\t2f\\n\"\n \t\t\"1:\tldmia\t%0!,\t{r0-r7}\\n\"\n \t\t\"\tstmia\t%1!,\t{r0-r7}\\n\"\n \t\t\"\tsub\t%1,\t#32\\n\"\n \t\t\"\tsubs\t%2,\t#1\\n\"\n \t\t\"\tbne\t1b\\n\"\n-\t\t\"\tcmp\t%3,\t#0\\n\"\n-\t\t\"\tbeq\t3f\\n\"\n-\t\t\"2:\tldr\t%2,\t[%0],\t#4\\n\"\n+\t\t\"2:\tcmp\t%3,\t#0\\n\"\n+\t\t\"\tbeq\t4f\\n\"\n+\t\t\"3:\tldr\t%2,\t[%0],\t#4\\n\"\n \t\t\"\tstr\t%2,\t[%1]\\n\"\n \t\t\"\tsubs\t%3,\t#1\\n\"\n-\t\t\"\tbne\t2b\\n\"\n-\t\t\"3:\tnop\\n\"\n+\t\t\"\tbne\t3b\\n\"\n+\t\t\"4:\tnop\\n\"\n \t\t: \"+r\"(src), \"+r\"(dst), \"+r\"(loops32), \"+r\"(loops4) :\n \t\t: \"r0\", \"r1\", \"r2\", \"r3\", \"r4\", \"r5\", \"r6\", \"r7\", \"cc\");\n }\n","prefixes":["U-Boot","v2","05/19"]}