{"id":818104,"url":"http://patchwork.ozlabs.org/api/patches/818104/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-8-git-send-email-tien.fong.chee@intel.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506328815-23733-8-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:03","name":"[U-Boot,v2,07/19] fdt: Add compatible strings for Arria 10","commit_ref":"eb57c0be14d114c7d0965918154fdfb414634108","pull_url":null,"state":"accepted","archived":false,"hash":"1f8915757c10c1375a64943c2b92edf3ecc1ea56","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/?format=json","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-8-git-send-email-tien.fong.chee@intel.com/mbox/","series":[{"id":4901,"url":"http://patchwork.ozlabs.org/api/series/4901/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4901","date":"2017-09-25T08:39:56","name":"Add FPGA, SDRAM, SPL loads U-boot & booting to console","version":2,"mbox":"http://patchwork.ozlabs.org/series/4901/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/818104/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/818104/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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25 Sep 2017 01:40:34 -0700"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,435,1500966000\"; d=\"scan'208\";a=\"155080120\"","From":"tien.fong.chee@intel.com","To":"u-boot@lists.denx.de","Date":"Mon, 25 Sep 2017 16:40:03 +0800","Message-Id":"<1506328815-23733-8-git-send-email-tien.fong.chee@intel.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>","Cc":"Marek Vasut , Tien Fong Chee , \n\tChing Liang See ,\n\tTien Fong , \n\tWestergteen Dalon ","Subject":"[U-Boot] [PATCH v2 07/19] fdt: Add compatible strings for Arria 10","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Tien Fong Chee \n\nAdd compatible strings for Intel Arria 10 SoCFPGA device.\n\nSigned-off-by: Tien Fong Chee \n---\n include/fdtdec.h | 2 ++\n lib/fdtdec.c | 2 ++\n 2 files changed, 4 insertions(+)","diff":"diff --git a/include/fdtdec.h b/include/fdtdec.h\nindex 4a0947c..095ff36 100644\n--- a/include/fdtdec.h\n+++ b/include/fdtdec.h\n@@ -157,6 +157,8 @@ enum fdt_compat_id {\n \tCOMPAT_ALTERA_SOCFPGA_F2SDR0, /* SoCFPGA fpga2SDRAM0 bridge */\n \tCOMPAT_ALTERA_SOCFPGA_F2SDR1, /* SoCFPGA fpga2SDRAM1 bridge */\n \tCOMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */\n+\tCOMPAT_ALTERA_SOCFPGA_FPGA0,\t\t/* SOCFPGA FPGA manager */\n+\tCOMPAT_ALTERA_SOCFPGA_NOC,\t\t/* SOCFPGA Arria 10 NOC */\n \n \tCOMPAT_COUNT,\n };\ndiff --git a/lib/fdtdec.c b/lib/fdtdec.c\nindex 107a892..03ff75e 100644\n--- a/lib/fdtdec.c\n+++ b/lib/fdtdec.c\n@@ -70,6 +70,8 @@ static const char * const compat_names[COMPAT_COUNT] = {\n \tCOMPAT(ALTERA_SOCFPGA_F2SDR0, \"altr,socfpga-fpga2sdram0-bridge\"),\n \tCOMPAT(ALTERA_SOCFPGA_F2SDR1, \"altr,socfpga-fpga2sdram1-bridge\"),\n \tCOMPAT(ALTERA_SOCFPGA_F2SDR2, \"altr,socfpga-fpga2sdram2-bridge\"),\n+\tCOMPAT(ALTERA_SOCFPGA_FPGA0, \"altr,socfpga-a10-fpga-mgr\"),\n+\tCOMPAT(ALTERA_SOCFPGA_NOC, \"altr,socfpga-a10-noc\"),\n };\n \n const char *fdtdec_get_compatible(enum fdt_compat_id id)\n","prefixes":["U-Boot","v2","07/19"]}