{"id":818102,"url":"http://patchwork.ozlabs.org/api/patches/818102/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-5-git-send-email-tien.fong.chee@intel.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506328815-23733-5-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:00","name":"[U-Boot,v2,04/19] arm: socfpga: Add Arria 10 SoCFPGA programming interface","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"09db3a8f3ff8df139237005b91ef30d6dcb2fc8b","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/?format=json","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-5-git-send-email-tien.fong.chee@intel.com/mbox/","series":[{"id":4901,"url":"http://patchwork.ozlabs.org/api/series/4901/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4901","date":"2017-09-25T08:39:56","name":"Add FPGA, SDRAM, SPL loads U-boot & booting to console","version":2,"mbox":"http://patchwork.ozlabs.org/series/4901/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/818102/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/818102/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0yKR05qDz9tX3\n\tfor ;\n\tMon, 25 Sep 2017 18:43:22 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid C1D31C21FC1; Mon, 25 Sep 2017 08:41:29 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 201B3C21FC2;\n\tMon, 25 Sep 2017 08:40:43 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 26C95C21DED; Mon, 25 Sep 2017 08:40:35 +0000 (UTC)","from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 53E37C21F85\n\tfor ; Mon, 25 Sep 2017 08:40:30 +0000 (UTC)","from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Sep 2017 01:40:29 -0700","from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.95])\n\tby fmsmga005.fm.intel.com with ESMTP; 25 Sep 2017 01:40:27 -0700"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,435,1500966000\"; d=\"scan'208\";a=\"155080092\"","From":"tien.fong.chee@intel.com","To":"u-boot@lists.denx.de","Date":"Mon, 25 Sep 2017 16:40:00 +0800","Message-Id":"<1506328815-23733-5-git-send-email-tien.fong.chee@intel.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>","Cc":"Marek Vasut , Tien Fong Chee , \n\tChing Liang See ,\n\tTien Fong , \n\tWestergteen Dalon ","Subject":"[U-Boot] [PATCH v2 04/19] arm: socfpga: Add Arria 10 SoCFPGA\n\tprogramming interface","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Tien Fong Chee \n\nAdd code necessary into the FPGA driver framework in U-Boot\nso it can be used via the 'fpga' command for programing Arria 10\nSoCFPGA.\n\nSigned-off-by: Tien Fong Chee \n---\n cmd/fpga.c | 2 +-\n drivers/fpga/altera.c | 39 +++++++++++++++++++++++++++++++--------\n drivers/fpga/fpga.c | 8 ++++++++\n include/fpga.h | 2 ++\n 4 files changed, 42 insertions(+), 9 deletions(-)","diff":"diff --git a/cmd/fpga.c b/cmd/fpga.c\nindex ac6f504..3cb0bcd 100644\n--- a/cmd/fpga.c\n+++ b/cmd/fpga.c\n@@ -363,7 +363,7 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga,\n \t \"(Xilinx only)\\n\"\n #endif\n #if defined(CONFIG_CMD_FPGA_LOADFS)\n-\t \"Load device from filesystem (FAT by default) (Xilinx only)\\n\"\n+\t \"Load device from filesystem (FAT by default)\\n\"\n \t \" loadfs [dev] [address] [image size] [blocksize] \\n\"\n \t \" [] \\n\"\n #endif\ndiff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c\nindex 135a357..e2bee99 100644\n--- a/drivers/fpga/altera.c\n+++ b/drivers/fpga/altera.c\n@@ -23,25 +23,31 @@ static const struct altera_fpga {\n \tenum altera_family\tfamily;\n \tconst char\t\t*name;\n \tint\t\t\t(*load)(Altera_desc *, const void *, size_t);\n+\tint (*loadfs)(Altera_desc *, const void *, size_t, fpga_fs_info *);\n \tint\t\t\t(*dump)(Altera_desc *, const void *, size_t);\n \tint\t\t\t(*info)(Altera_desc *);\n } altera_fpga[] = {\n #if defined(CONFIG_FPGA_ACEX1K)\n-\t{ Altera_ACEX1K, \"ACEX1K\", ACEX1K_load, ACEX1K_dump, ACEX1K_info },\n-\t{ Altera_CYC2, \"ACEX1K\", ACEX1K_load, ACEX1K_dump, ACEX1K_info },\n+\t{ Altera_ACEX1K, \"ACEX1K\", ACEX1K_load, NULL, ACEX1K_dump,\n+\t ACEX1K_info },\n+\t{ Altera_CYC2, \"ACEX1K\", ACEX1K_load, NULL, ACEX1K_dump,\n+\t ACEX1K_info },\n #elif defined(CONFIG_FPGA_CYCLON2)\n-\t{ Altera_ACEX1K, \"CycloneII\", CYC2_load, CYC2_dump, CYC2_info },\n-\t{ Altera_CYC2, \"CycloneII\", CYC2_load, CYC2_dump, CYC2_info },\n+\t{ Altera_ACEX1K, \"CycloneII\", CYC2_load, NULL, CYC2_dump, CYC2_info },\n+\t{ Altera_CYC2, \"CycloneII\", CYC2_load, NULL, CYC2_dump, CYC2_info },\n #endif\n #if defined(CONFIG_FPGA_STRATIX_II)\n-\t{ Altera_StratixII, \"StratixII\", StratixII_load,\n+\t{ Altera_StratixII, \"StratixII\", StratixII_load, NULL,\n \t StratixII_dump, StratixII_info },\n #endif\n #if defined(CONFIG_FPGA_STRATIX_V)\n-\t{ Altera_StratixV, \"StratixV\", stratixv_load, NULL, NULL },\n+\t{ Altera_StratixV, \"StratixV\", stratixv_load, NULL, NULL, NULL },\n #endif\n-#if defined(CONFIG_FPGA_SOCFPGA)\n-\t{ Altera_SoCFPGA, \"SoC FPGA\", socfpga_load, NULL, NULL },\n+#if defined(CONFIG_FPGA_SOCFPGA) && defined(CONFIG_CMD_FPGA_LOADFS)\n+\t{ Altera_SoCFPGA, \"SoC FPGA\", socfpga_load, socfpga_loadfs, NULL,\n+\t NULL },\n+#elif defined(CONFIG_FPGA_SOCFPGA)\n+\t{ Altera_SoCFPGA, \"SoC FPGA\", socfpga_load, NULL, NULL, NULL },\n #endif\n };\n \n@@ -174,3 +180,20 @@ int altera_info(Altera_desc *desc)\n \n \treturn FPGA_SUCCESS;\n }\n+\n+#if defined(CONFIG_CMD_FPGA_LOADFS)\n+int altera_loadfs(Altera_desc *desc, const void *buf, size_t bsize,\n+\t\t fpga_fs_info *fpga_fsinfo)\n+{\n+\tconst struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);\n+\n+\tif (!fpga)\n+\t\treturn FPGA_FAIL;\n+\n+\tdebug_cond(FPGA_DEBUG, \"%s: Launching the %s FS Loader...\\n\",\n+\t\t __func__, fpga->name);\n+\tif (fpga->loadfs)\n+\t\treturn fpga->loadfs(desc, buf, bsize, fpga_fsinfo);\n+\treturn 0;\n+}\n+#endif\ndiff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c\nindex e0fb1b4..42e901e 100644\n--- a/drivers/fpga/fpga.c\n+++ b/drivers/fpga/fpga.c\n@@ -198,6 +198,14 @@ int fpga_fsload(int devnum, const void *buf, size_t size,\n \t\t\tfpga_no_sup((char *)__func__, \"Xilinx devices\");\n #endif\n \t\t\tbreak;\n+#if defined(CONFIG_FPGA_ALTERA)\n+\t\tcase fpga_altera:\n+\t\t\tret_val = altera_loadfs(desc->devdesc, buf, size,\n+\t\t\t\t\t\tfpga_fsinfo);\n+#else\n+\t\t\tfpga_no_sup((char *)__func__, \"Altera devices\");\n+#endif\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tprintf(\"%s: Invalid or unsupported device type %d\\n\",\n \t\t\t __func__, desc->devtype);\ndiff --git a/include/fpga.h b/include/fpga.h\nindex d768fb1..8920016 100644\n--- a/include/fpga.h\n+++ b/include/fpga.h\n@@ -56,8 +56,10 @@ int fpga_count(void);\n const fpga_desc *const fpga_get_desc(int devnum);\n int fpga_load(int devnum, const void *buf, size_t bsize,\n \t bitstream_type bstype);\n+#if defined(CONFIG_CMD_FPGA_LOADFS)\n int fpga_fsload(int devnum, const void *buf, size_t size,\n \t\tfpga_fs_info *fpga_fsinfo);\n+#endif\n int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,\n \t\t bitstream_type bstype);\n int fpga_dump(int devnum, const void *buf, size_t bsize);\n","prefixes":["U-Boot","v2","04/19"]}