{"id":818101,"url":"http://patchwork.ozlabs.org/api/patches/818101/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-3-git-send-email-tien.fong.chee@intel.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506328815-23733-3-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:39:58","name":"[U-Boot,v2,02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"051e32427ec4f4fc15bd2ad693cd4b15d36bc6d9","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/?format=json","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-3-git-send-email-tien.fong.chee@intel.com/mbox/","series":[{"id":4901,"url":"http://patchwork.ozlabs.org/api/series/4901/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4901","date":"2017-09-25T08:39:56","name":"Add FPGA, SDRAM, SPL loads U-boot & booting to console","version":2,"mbox":"http://patchwork.ozlabs.org/series/4901/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/818101/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/818101/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0yHm5pRMz9tX3\n\tfor ;\n\tMon, 25 Sep 2017 18:41:56 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 52850C21FE0; Mon, 25 Sep 2017 08:40:55 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 61190C21F4E;\n\tMon, 25 Sep 2017 08:40:29 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 672E3C21D78; Mon, 25 Sep 2017 08:40:26 +0000 (UTC)","from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 98021C21C26\n\tfor ; Mon, 25 Sep 2017 08:40:25 +0000 (UTC)","from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Sep 2017 01:40:25 -0700","from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.95])\n\tby fmsmga005.fm.intel.com with ESMTP; 25 Sep 2017 01:40:23 -0700"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,435,1500966000\"; d=\"scan'208\";a=\"155080072\"","From":"tien.fong.chee@intel.com","To":"u-boot@lists.denx.de","Date":"Mon, 25 Sep 2017 16:39:58 +0800","Message-Id":"<1506328815-23733-3-git-send-email-tien.fong.chee@intel.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>","Cc":"Marek Vasut , Tien Fong Chee , \n\tChing Liang See ,\n\tTien Fong , \n\tWestergteen Dalon ","Subject":"[U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF\n\tproperties at Arria 10 FPGA manager","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Tien Fong Chee \n\nThis patch adds description on properties about location of FPGA RBFs are\nstored, type and functionality of RBF used to configure FPGA.\n\nSigned-off-by: Tien Fong Chee \n---\n doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11 +++++++++++\n 1 file changed, 11 insertions(+)","diff":"diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\nindex 2fd8e7a..7abb746 100644\n--- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n@@ -7,6 +7,14 @@ Required properties:\n - The second index is for writing FPGA configuration data.\n - resets : Phandle and reset specifier for the device's reset.\n - clocks : Clocks used by the device.\n+- bitstream_periph : FPGA peripheral raw binary file which is used to\n+ initialize FPGA IOs, PLL, IO48 and DDR.\n+- bitstream_core : FPGA core raw binary file contains FPGA design which is used\n+ to program FPGA CRAM and ERAM.\n+- bitstream_devpart : Partition of flash device where bitstream files are\n+\t\t stored.\n+ - dev is flash device number, part is flash\n+ device partition.\n \n Example:\n \n@@ -16,4 +24,7 @@ Example:\n \t\t 0xffcfe400 0x20>;\n \t\tclocks = <&l4_mp_clk>;\n \t\tresets = <&rst FPGAMGR_RESET>;\n+\t\tbitstream_periph = \"ghrd_10as066n2.periph.rbf.mkimage\";\n+\t\tbitstream_core = \"ghrd_10as066n2.core.rbf.mkimage\";\n+\t\tbitstream_devpart = \"0:1\";\n \t};\n","prefixes":["U-Boot","v2","02/19"]}