{"id":817888,"url":"http://patchwork.ozlabs.org/api/patches/817888/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170924105924.23923-2-vigneshr@ti.com/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170924105924.23923-2-vigneshr@ti.com>","list_archive_url":null,"date":"2017-09-24T10:59:20","name":"[v3,1/5] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"e3ecfb01b85f55c37fef1ebd66f9a2612f5233c8","submitter":{"id":65039,"url":"http://patchwork.ozlabs.org/api/people/65039/?format=json","name":"Raghavendra, Vignesh","email":"vigneshr@ti.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170924105924.23923-2-vigneshr@ti.com/mbox/","series":[{"id":4810,"url":"http://patchwork.ozlabs.org/api/series/4810/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=4810","date":"2017-09-24T10:59:20","name":"K2G: Add QSPI support","version":3,"mbox":"http://patchwork.ozlabs.org/series/4810/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/817888/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/817888/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"VOi+YARy\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0PQM1txgz9sDB\n\tfor ;\n\tSun, 24 Sep 2017 21:00:43 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752158AbdIXLAR (ORCPT\n\t);\n\tSun, 24 Sep 2017 07:00:17 -0400","from lelnx194.ext.ti.com ([198.47.27.80]:23692 \"EHLO\n\tlelnx194.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752041AbdIXLAQ (ORCPT\n\t); Sun, 24 Sep 2017 07:00:16 -0400","from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8OAxBKG019913; \n\tSun, 24 Sep 2017 05:59:11 -0500","from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8OAxBmV005325; \n\tSun, 24 Sep 2017 05:59:11 -0500","from DLEE108.ent.ti.com (157.170.170.38) by DLEE114.ent.ti.com\n\t(157.170.170.25) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tSun, 24 Sep 2017 05:59:11 -0500","from dflp33.itg.ti.com (10.64.6.16) by DLEE108.ent.ti.com\n\t(157.170.170.38) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Sun, 24 Sep 2017 05:59:11 -0500","from a0132425.india.ti.com (ileax41-snat.itg.ti.com\n\t[10.172.224.153])\n\tby dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8OAx4DE027688;\n\tSun, 24 Sep 2017 05:59:08 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506250751;\n\tbh=k8p/LqUqVDVFSLOJH+ZUps60729d8JHs9HdJk1vHZ9c=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=VOi+YARykhNM0bzjP6yGNdxbS+Y/1aOaJeMlR7i3CPb1OIAIQ7CzbTdu9948iu/PN\n\t0x6fYFEen6yrESFMKXBZLAQlPPePFI4Zv9nH+3mTj2rOFHL09+LMMSeqCEkYmnpZon\n\th2kE8usUj2EBJZxKUnQkC2QZH1sE6UVtxzZgEZ+g=","From":"Vignesh R ","To":"Marek Vasut ,\n\tCyrille Pitchen ","CC":"David Woodhouse ,\n\tBrian Norris ,\n\tBoris Brezillon ,\n\tRob Herring ,\n\t, ,\n\t, Vignesh R ,\n\tlinux-arm-kernel ","Subject":"[PATCH v3 1/5] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC\n\tspecific compatible","Date":"Sun, 24 Sep 2017 16:29:20 +0530","Message-ID":"<20170924105924.23923-2-vigneshr@ti.com>","X-Mailer":"git-send-email 2.14.1","In-Reply-To":"<20170924105924.23923-1-vigneshr@ti.com>","References":"<20170924105924.23923-1-vigneshr@ti.com>","MIME-Version":"1.0","Content-Type":"text/plain","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"Update binding documentation to add a new compatible for TI 66AK2G SoC,\nto handle TI SoC specific quirks in the driver.\n\nSigned-off-by: Vignesh R \nAcked-by: Rob Herring \n---\n Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)","diff":"diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt\nindex f248056da24c..7dbe3bd9ac56 100644\n--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt\n+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt\n@@ -1,7 +1,9 @@\n * Cadence Quad SPI controller\n \n Required properties:\n-- compatible : Should be \"cdns,qspi-nor\".\n+- compatible : should be one of the following:\n+\tGeneric default - \"cdns,qspi-nor\".\n+\tFor TI 66AK2G SoC - \"ti,k2g-qspi\", \"cdns,qspi-nor\".\n - reg : Contains two entries, each of which is a tuple consisting of a\n \tphysical address and length. The first entry is the address and\n \tlength of the controller register set. The second entry is the\n","prefixes":["v3","1/5"]}