{"id":817867,"url":"http://patchwork.ozlabs.org/api/patches/817867/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506232825-27448-5-git-send-email-uri.mashiach@compulab.co.il/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506232825-27448-5-git-send-email-uri.mashiach@compulab.co.il>","list_archive_url":null,"date":"2017-09-24T06:00:25","name":"[U-Boot,4/4] arm: imx7d: add support for Compulab cl-som-imx7","commit_ref":null,"pull_url":null,"state":"awaiting-upstream","archived":false,"hash":"50631e24d25cd1a86ae03725eaeea300a4e6f51b","submitter":{"id":67462,"url":"http://patchwork.ozlabs.org/api/people/67462/?format=json","name":"Uri Mashiach","email":"uri.mashiach@compulab.co.il"},"delegate":{"id":1693,"url":"http://patchwork.ozlabs.org/api/users/1693/?format=json","username":"sbabic","first_name":"Stefano","last_name":"Babic","email":"sbabic@denx.de"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506232825-27448-5-git-send-email-uri.mashiach@compulab.co.il/mbox/","series":[{"id":4801,"url":"http://patchwork.ozlabs.org/api/series/4801/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4801","date":"2017-09-24T06:00:21","name":"cl-som-imx7: initial support","version":1,"mbox":"http://patchwork.ozlabs.org/series/4801/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/817867/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/817867/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none 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(uri-ipc.compulab.local\n\t[192.168.11.218])\n\tby zimbra-mta.compulab.co.il (Postfix) with ESMTP id 1CC0E48109D;\n\tSun, 24 Sep 2017 09:01:49 +0300 (IDT)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=SPF_HELO_PASS, T_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=compulab.co.il; s=default;\n\th=References:In-Reply-To:Message-Id:Date:Subject\n\t:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type:\n\tContent-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:\n\tList-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive;\n\tbh=V/LA0g5JeltpCwKyhhaRr+a4hSY5Ar9gZKmvwbpoUeU=;\n\tb=pnIHXxzyDH/apWOoAY6qhTYph\n\t+KItceAMWIkJYdUhhWqpj7+8z4fiBH8TLwQcD8SA09CaS/DY8vteirqOEw4Lei2J1WpkgTC9oGUD9\n\t6+AjnkFJNtgctJdLMPTIWXcbynz7d0tTsW9QAUyzH1zdPTNSlyuxeSXYwE3oVEINmfM2j4HpDulXr\n\tZg2z1ompfBDcyo2+A2uvKDMyQ4uaBKliyaNfEtNuMLYKb0nVrbGimuSKbb5/I7uWxjTb+6i+HoyDV\n\tZz7rxHLZgeWASpsbRC+MDw5Y6foVWAyKMzWzaywIiOyoPfAbX5Cl18CoQ8wU/Bv6YzRa+Tt9sqJNA\n\tgbgOimwtw==;","X-Virus-Scanned":"amavisd-new at zimbra-mta.compulab.co.il","From":"Uri Mashiach ","To":"Stefano Babic ","Date":"Sun, 24 Sep 2017 09:00:25 +0300","Message-Id":"<1506232825-27448-5-git-send-email-uri.mashiach@compulab.co.il>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506232825-27448-1-git-send-email-uri.mashiach@compulab.co.il>","References":"<1506232825-27448-1-git-send-email-uri.mashiach@compulab.co.il>","X-AntiAbuse":["This header was added to track abuse,\n\tplease include it with any abuse report","Primary Hostname - softlayer.compulab.co.il","Original Domain - lists.denx.de","Originator/Caller UID/GID - [47 12] / [47 12]","Sender Address Domain - compulab.co.il"],"X-Get-Message-Sender-Via":"softlayer.compulab.co.il: acl_c_recent_authed_mail_ips_text_entry:\n\turi.mashiach@compulab.co.il|compulab.co.il","X-Authenticated-Sender":"softlayer.compulab.co.il: uri.mashiach@compulab.co.il","Cc":"Fabio Estevam , u-boot@lists.denx.de","Subject":"[U-Boot] [PATCH 4/4] arm: imx7d: add support for Compulab\n\tcl-som-imx7","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Ilya Ledvich \n\nAdd initial support for Compulab cl-som-imx7 SoM.\nThe initial support includes:\n - MMC\n - eMMC\n - SPI flash\n - I2C\n - FEC\n - USB\n - Serial console\n\nSigned-off-by: Ilya Ledvich \n---\n arch/arm/mach-imx/mx7/Kconfig | 8 +\n board/compulab/cl-som-imx7/Kconfig | 28 +++\n board/compulab/cl-som-imx7/MAINTAINERS | 6 +\n board/compulab/cl-som-imx7/Makefile | 17 ++\n board/compulab/cl-som-imx7/cl-som-imx7.c | 331 +++++++++++++++++++++++++++++++\n board/compulab/cl-som-imx7/common.c | 46 +++++\n board/compulab/cl-som-imx7/common.h | 32 +++\n board/compulab/cl-som-imx7/mux.c | 142 +++++++++++++\n board/compulab/cl-som-imx7/spl.c | 211 ++++++++++++++++++++\n configs/cl-som-imx7_defconfig | 54 +++++\n include/configs/cl-som-imx7.h | 192 ++++++++++++++++++\n 11 files changed, 1067 insertions(+)\n create mode 100644 board/compulab/cl-som-imx7/Kconfig\n create mode 100644 board/compulab/cl-som-imx7/MAINTAINERS\n create mode 100644 board/compulab/cl-som-imx7/Makefile\n create mode 100644 board/compulab/cl-som-imx7/cl-som-imx7.c\n create mode 100644 board/compulab/cl-som-imx7/common.c\n create mode 100644 board/compulab/cl-som-imx7/common.h\n create mode 100644 board/compulab/cl-som-imx7/mux.c\n create mode 100644 board/compulab/cl-som-imx7/spl.c\n create mode 100644 configs/cl-som-imx7_defconfig\n create mode 100644 include/configs/cl-som-imx7.h","diff":"diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig\nindex aea8526..365501d 100644\n--- a/arch/arm/mach-imx/mx7/Kconfig\n+++ b/arch/arm/mach-imx/mx7/Kconfig\n@@ -18,6 +18,13 @@ choice\n \tprompt \"MX7 board select\"\n \toptional\n \n+config TARGET_CL_SOM_IMX7\n+\tbool \"CL-SOM-iMX7\"\n+\tselect MX7D\n+\tselect DM\n+\tselect DM_THERMAL\n+\tselect SUPPORT_SPL\n+\n config TARGET_MX7DSABRESD\n \tbool \"mx7dsabresd\"\n \tselect BOARD_LATE_INIT\n@@ -51,6 +58,7 @@ endchoice\n config SYS_SOC\n \tdefault \"mx7\"\n \n+source \"board/compulab/cl-som-imx7/Kconfig\"\n source \"board/freescale/mx7dsabresd/Kconfig\"\n source \"board/technexion/pico-imx7d/Kconfig\"\n source \"board/toradex/colibri_imx7/Kconfig\"\ndiff --git a/board/compulab/cl-som-imx7/Kconfig b/board/compulab/cl-som-imx7/Kconfig\nnew file mode 100644\nindex 0000000..6d69cf3\n--- /dev/null\n+++ b/board/compulab/cl-som-imx7/Kconfig\n@@ -0,0 +1,28 @@\n+if TARGET_CL_SOM_IMX7\n+\n+config SYS_BOARD\n+\tdefault \"cl-som-imx7\"\n+\n+config SYS_VENDOR\n+\tdefault \"compulab\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"cl-som-imx7\"\n+\n+config SYS_MMC_DEV\n+\tint\n+\tdefault 0\n+\n+config SYS_USB_DEV\n+\tint\n+\tdefault 0\n+\n+config SYS_MMC_IMG_LOAD_PART\n+\tint\n+\tdefault 1\n+\n+config SYS_USB_IMG_LOAD_PART\n+\tint\n+\tdefault 1\n+\n+endif\ndiff --git a/board/compulab/cl-som-imx7/MAINTAINERS b/board/compulab/cl-som-imx7/MAINTAINERS\nnew file mode 100644\nindex 0000000..2b917a5\n--- /dev/null\n+++ b/board/compulab/cl-som-imx7/MAINTAINERS\n@@ -0,0 +1,6 @@\n+CL-SOM-IMX7 BOARD\n+M:\tUri Mashiach \n+S:\tMaintained\n+F:\tboard/compulab/cl-som-imx7\n+F:\tinclude/configs/cl-som-imx7.h\n+F:\tconfigs/cl-som-imx7_defconfig\ndiff --git a/board/compulab/cl-som-imx7/Makefile b/board/compulab/cl-som-imx7/Makefile\nnew file mode 100644\nindex 0000000..8f0e068\n--- /dev/null\n+++ b/board/compulab/cl-som-imx7/Makefile\n@@ -0,0 +1,17 @@\n+#\n+# Makefile\n+#\n+# (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com\n+#\n+# Author: Uri Mashiach \n+#\n+# SPDX-License-Identifier: GPL-2.0+\n+#\n+\n+obj-y := mux.o common.o\n+\n+ifdef CONFIG_SPL_BUILD\n+obj-y += spl.o\n+else\n+obj-y += cl-som-imx7.o\n+endif\ndiff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c\nnew file mode 100644\nindex 0000000..2957180\n--- /dev/null\n+++ b/board/compulab/cl-som-imx7/cl-som-imx7.c\n@@ -0,0 +1,331 @@\n+/*\n+ * U-Boot board functions for CompuLab CL-SOM-iMX7 module\n+ *\n+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com\n+ *\n+ * Author: Uri Mashiach \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \"../common/eeprom.h\"\n+#include \"common.h\"\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+#ifdef CONFIG_SYS_I2C_MXC\n+\n+#define I2C_PAD_CTRL\t\t(PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \\\n+\t\t\t\tPAD_CTL_HYS)\n+\n+#define CL_SOM_IMX7_GPIO_I2C2_SCL\tIMX_GPIO_NR(1, 6)\n+#define CL_SOM_IMX7_GPIO_I2C2_SDA\tIMX_GPIO_NR(1, 7)\n+\n+static struct i2c_pads_info cl_som_imx7_i2c_pad_info2 = {\n+\t.scl = {\n+\t\t.i2c_mode = MX7D_PAD_GPIO1_IO06__I2C2_SCL |\n+\t\t\tMUX_PAD_CTRL(I2C_PAD_CTRL),\n+\t\t.gpio_mode = MX7D_PAD_GPIO1_IO06__GPIO1_IO6 |\n+\t\t\tMUX_PAD_CTRL(I2C_PAD_CTRL),\n+\t\t.gp = CL_SOM_IMX7_GPIO_I2C2_SCL,\n+\t},\n+\t.sda = {\n+\t\t.i2c_mode = MX7D_PAD_GPIO1_IO07__I2C2_SDA |\n+\t\t\tMUX_PAD_CTRL(I2C_PAD_CTRL),\n+\t\t.gpio_mode = MX7D_PAD_GPIO1_IO07__GPIO1_IO7 |\n+\t\t\tMUX_PAD_CTRL(I2C_PAD_CTRL),\n+\t\t.gp = CL_SOM_IMX7_GPIO_I2C2_SDA,\n+\t},\n+};\n+\n+/*\n+ * cl_som_imx7_setup_i2c() - I2C pinmux configuration.\n+ */\n+static void cl_som_imx7_setup_i2c(void)\n+{\n+\tsetup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &cl_som_imx7_i2c_pad_info2);\n+}\n+#else /* !CONFIG_SYS_I2C_MXC */\n+static void cl_som_imx7_setup_i2c(void) {}\n+#endif /* CONFIG_SYS_I2C_MXC */\n+\n+int dram_init(void)\n+{\n+\tgd->ram_size = imx_ddr_size();\n+\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_FSL_ESDHC\n+\n+#define CL_SOM_IMX7_GPIO_USDHC3_PWR\tIMX_GPIO_NR(6, 11)\n+\n+static struct fsl_esdhc_cfg cl_som_imx7_usdhc_cfg[3] = {\n+\t{USDHC1_BASE_ADDR, 0, 4},\n+\t{USDHC3_BASE_ADDR},\n+};\n+\n+int board_mmc_init(bd_t *bis)\n+{\n+\tint i, ret;\n+\t/*\n+\t * According to the board_mmc_init() the following map is done:\n+\t * (U-boot device node) (Physical Port)\n+\t * mmc0 USDHC1\n+\t * mmc2 USDHC3 (eMMC)\n+\t */\n+\tfor (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {\n+\t\tswitch (i) {\n+\t\tcase 0:\n+\t\t\tcl_som_imx7_usdhc1_pads_set();\n+\t\t\tgpio_request(CL_SOM_IMX7_GPIO_USDHC1_CD, \"usdhc1_cd\");\n+\t\t\tcl_som_imx7_usdhc_cfg[0].sdhc_clk =\n+\t\t\t\tmxc_get_clock(MXC_ESDHC_CLK);\n+\t\t\tbreak;\n+\t\tcase 1:\n+\t\t\tcl_som_imx7_usdhc3_emmc_pads_set();\n+\t\t\tgpio_request(CL_SOM_IMX7_GPIO_USDHC3_PWR, \"usdhc3_pwr\");\n+\t\t\tgpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 0);\n+\t\t\tudelay(500);\n+\t\t\tgpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 1);\n+\t\t\tcl_som_imx7_usdhc_cfg[1].sdhc_clk =\n+\t\t\t\tmxc_get_clock(MXC_ESDHC3_CLK);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tprintf(\"Warning: you configured more USDHC controllers \"\n+\t\t\t\t\"(%d) than supported by the board\\n\", i + 1);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tret = fsl_esdhc_initialize(bis, &cl_som_imx7_usdhc_cfg[i]);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+#endif /* CONFIG_FSL_ESDHC */\n+\n+#ifdef CONFIG_FEC_MXC\n+\n+#define CL_SOM_IMX7_ETH1_PHY_NRST\tIMX_GPIO_NR(1, 4)\n+\n+/*\n+ * cl_som_imx7_rgmii_rework() - Ethernet PHY configuration.\n+ */\n+static void cl_som_imx7_rgmii_rework(struct phy_device *phydev)\n+{\n+\tunsigned short val;\n+\n+\t/* Ar8031 phy SmartEEE feature cause link status generates glitch,\n+\t * which cause ethernet link down/up issue, so disable SmartEEE\n+\t */\n+\tphy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);\n+\tphy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);\n+\tphy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);\n+\tval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);\n+\tval &= ~(0x1 << 8);\n+\tphy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);\n+\n+\t/* To enable AR8031 ouput a 125MHz clk from CLK_25M */\n+\tphy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);\n+\tphy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);\n+\tphy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);\n+\n+\tval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);\n+\tval &= 0xffe3;\n+\tval |= 0x18;\n+\tphy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);\n+\n+\t/* introduce tx clock delay */\n+\tphy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);\n+\tval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);\n+\tval |= 0x0100;\n+\tphy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);\n+}\n+\n+int board_phy_config(struct phy_device *phydev)\n+{\n+\tcl_som_imx7_rgmii_rework(phydev);\n+\n+\tif (phydev->drv->config)\n+\t\tphydev->drv->config(phydev);\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * cl_som_imx7_handle_mac_address() - set Ethernet MAC address environment.\n+ *\n+ * @env_var: MAC address environment variable\n+ * @eeprom_bus: I2C bus of the environment EEPROM\n+ *\n+ * @return: 0 on success, < 0 on failure\n+ */\n+static int cl_som_imx7_handle_mac_address(char *env_var, uint eeprom_bus)\n+{\n+\tint ret;\n+\tunsigned char enetaddr[6];\n+\n+\tret = eth_env_get_enetaddr(env_var, enetaddr);\n+\tif (ret)\n+\t\treturn 0;\n+\n+\tret = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = is_valid_ethaddr(enetaddr);\n+\tif (!ret)\n+\t\treturn -1;\n+\n+\treturn eth_env_set_enetaddr(env_var, enetaddr);\n+}\n+\n+#define CL_SOM_IMX7_FEC_DEV_ID_PRI 0\n+\n+int board_eth_init(bd_t *bis)\n+{\n+\t/* set Ethernet MAC address environment */\n+\tcl_som_imx7_handle_mac_address(\"ethaddr\", CONFIG_SYS_I2C_EEPROM_BUS);\n+\t/* Ethernet interface pinmux configuration */\n+\tcl_som_imx7_phy1_rst_pads_set();\n+\tcl_som_imx7_fec1_pads_set();\n+\t/* PHY reset */\n+\tgpio_request(CL_SOM_IMX7_ETH1_PHY_NRST, \"eth1_phy_nrst\");\n+\tgpio_direction_output(CL_SOM_IMX7_ETH1_PHY_NRST, 0);\n+\tmdelay(10);\n+\tgpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1);\n+\t/* MAC initialization */\n+\treturn fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI,\n+\t\t\t\t CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);\n+}\n+\n+/*\n+ * cl_som_imx7_setup_fec() - Ethernet MAC 1 clock configuration.\n+ * - ENET1 reference clock mode select.\n+ * - ENET1_TX_CLK output driver is disabled when configured for ALT1.\n+ */\n+static void cl_som_imx7_setup_fec(void)\n+{\n+\tstruct iomuxc_gpr_base_regs *const iomuxc_gpr_regs\n+\t\t= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;\n+\n+\t/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/\n+\tclrsetbits_le32(&iomuxc_gpr_regs->gpr[1],\n+\t\t\t(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |\n+\t\t\t IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);\n+\n+\tset_clk_enet(ENET_125MHz);\n+}\n+#else /* !CONFIG_FEC_MXC */\n+static void cl_som_imx7_setup_fec(void) {}\n+#endif /* CONFIG_FEC_MXC */\n+\n+#ifdef CONFIG_SPI\n+\n+static void cl_som_imx7_spi_init(void)\n+{\n+\tcl_som_imx7_espi1_pads_set();\n+}\n+#else /* !CONFIG_SPI */\n+static void cl_som_imx7_spi_init(void) {}\n+#endif /* CONFIG_SPI */\n+\n+int board_early_init_f(void)\n+{\n+\tcl_som_imx7_uart1_pads_set();\n+\tcl_som_imx7_usb_otg1_pads_set();\n+\n+\treturn 0;\n+}\n+\n+int board_init(void)\n+{\n+\t/* address of boot parameters */\n+\tgd->bd->bi_boot_params = PHYS_SDRAM + 0x100;\n+\tcl_som_imx7_setup_i2c();\n+\tcl_som_imx7_setup_fec();\n+\tcl_som_imx7_spi_init();\n+\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_POWER\n+#define I2C_PMIC\t0\n+int power_init_board(void)\n+{\n+\tstruct pmic *p;\n+\tint ret;\n+\tunsigned int reg, rev_id;\n+\n+\tret = power_pfuze3000_init(I2C_PMIC);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tp = pmic_get(\"PFUZE3000\");\n+\tret = pmic_probe(p);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tpmic_reg_read(p, PFUZE3000_DEVICEID, ®);\n+\tpmic_reg_read(p, PFUZE3000_REVID, &rev_id);\n+\tprintf(\"PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\\n\", reg, rev_id);\n+\n+\t/* disable Low Power Mode during standby mode */\n+\tpmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1);\n+\n+\treturn 0;\n+}\n+#endif /* CONFIG_POWER */\n+\n+/*\n+ * cl_som_imx7_setup_wdog() - watchdog configuration.\n+ * - Output WDOG_B signal to reset external pmic.\n+ * - Suspend the watchdog timer during low-power modes.\n+ */\n+void cl_som_imx7_setup_wdog(void)\n+{\n+\tstruct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;\n+\n+\tcl_som_imx7_wdog_pads_set();\n+\tset_wdog_reset(wdog);\n+ /*\n+\t* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),\n+\t* since we use PMIC_PWRON to reset the board.\n+\t*/\n+\tclrsetbits_le16(&wdog->wcr, 0, 0x10);\n+}\n+\n+int board_late_init(void)\n+{\n+\tenv_set(\"board_name\", \"CL-SOM-iMX7\");\n+\tcl_som_imx7_setup_wdog();\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tchar *mode;\n+\n+\tif (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))\n+\t\tmode = \"secure\";\n+\telse\n+\t\tmode = \"non-secure\";\n+\n+\tprintf(\"Board: CL-SOM-iMX7 in %s mode\\n\", mode);\n+\n+\treturn 0;\n+}\ndiff --git a/board/compulab/cl-som-imx7/common.c b/board/compulab/cl-som-imx7/common.c\nnew file mode 100644\nindex 0000000..5ee688a\n--- /dev/null\n+++ b/board/compulab/cl-som-imx7/common.c\n@@ -0,0 +1,46 @@\n+/*\n+ * SPL/U-Boot common functions for CompuLab CL-SOM-iMX7 module\n+ *\n+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com\n+ *\n+ * Author: Uri Mashiach \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include \n+#include \n+#include \n+#include \"common.h\"\n+\n+#ifdef CONFIG_SPI\n+\n+#define CL_SOM_IMX7_GPIO_SPI_CS\tIMX_GPIO_NR(4, 19)\n+\n+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)\n+{\n+\treturn CL_SOM_IMX7_GPIO_SPI_CS;\n+}\n+\n+#endif /* CONFIG_SPI */\n+\n+#ifdef CONFIG_FSL_ESDHC\n+\n+int board_mmc_getcd(struct mmc *mmc)\n+{\n+\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n+\tint ret = 0;\n+\n+\tswitch (cfg->esdhc_base) {\n+\tcase USDHC1_BASE_ADDR:\n+\t\tret = !gpio_get_value(CL_SOM_IMX7_GPIO_USDHC1_CD);\n+\t\tbreak;\n+\tcase USDHC3_BASE_ADDR:\n+\t\tret = 1; /* Assume uSDHC3 emmc is always present */\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+#endif /* CONFIG_FSL_ESDHC */\ndiff --git a/board/compulab/cl-som-imx7/common.h b/board/compulab/cl-som-imx7/common.h\nnew file mode 100644\nindex 0000000..72d96af\n--- /dev/null\n+++ b/board/compulab/cl-som-imx7/common.h\n@@ -0,0 +1,32 @@\n+/*\n+ * SPL/U-Boot common header file for CompuLab CL-SOM-iMX7 module\n+ *\n+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com\n+ *\n+ * Author: Uri Mashiach \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define PADS_SET_PROT(pads_array) void cl_som_imx7_##pads_array##_set(void)\n+\n+#ifdef CONFIG_FSL_ESDHC\n+#define CL_SOM_IMX7_GPIO_USDHC1_CD\tIMX_GPIO_NR(5, 0)\n+PADS_SET_PROT(usdhc1_pads);\n+#endif /* CONFIG_FSL_ESDHC */\n+PADS_SET_PROT(uart1_pads);\n+#ifdef CONFIG_SPI\n+PADS_SET_PROT(espi1_pads);\n+#endif /* CONFIG_SPI */\n+\n+#ifndef CONFIG_SPL_BUILD\n+#ifdef CONFIG_FSL_ESDHC\n+PADS_SET_PROT(usdhc3_emmc_pads);\n+#endif /* CONFIG_FSL_ESDHC */\n+#ifdef CONFIG_FEC_MXC\n+PADS_SET_PROT(phy1_rst_pads);\n+PADS_SET_PROT(fec1_pads);\n+#endif /* CONFIG_FEC_MXC */\n+PADS_SET_PROT(usb_otg1_pads);\n+PADS_SET_PROT(wdog_pads);\n+#endif /* !CONFIG_SPL_BUILD */\ndiff --git a/board/compulab/cl-som-imx7/mux.c b/board/compulab/cl-som-imx7/mux.c\nnew file mode 100644\nindex 0000000..82e8b9f\n--- /dev/null\n+++ b/board/compulab/cl-som-imx7/mux.c\n@@ -0,0 +1,142 @@\n+/*\n+ * SPL/U-Boot mux functions for CompuLab CL-SOM-iMX7 module\n+ *\n+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com\n+ *\n+ * Author: Uri Mashiach \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include \n+#include \n+#include \n+\n+#define PADS_SET(pads_array)\t\t\t\t\t\t \\\n+void cl_som_imx7_##pads_array##_set(void)\t\t\t\t \\\n+{\t\t\t\t\t\t\t\t\t \\\n+\timx_iomux_v3_setup_multiple_pads(pads_array, ARRAY_SIZE(pads_array)); \\\n+}\n+\n+#ifdef CONFIG_FSL_ESDHC\n+\n+#define USDHC_PAD_CTRL\t\t(PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \\\n+\t\t\t\tPAD_CTL_HYS | PAD_CTL_PUE | \\\n+\t\t\t\tPAD_CTL_PUS_PU47KOHM)\n+\n+static iomux_v3_cfg_t const usdhc1_pads[] = {\n+\tMX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\n+\tMX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+};\n+\n+PADS_SET(usdhc1_pads)\n+\n+#endif /* CONFIG_FSL_ESDHC */\n+\n+#define UART_PAD_CTRL\t\t(PAD_CTL_DSE_3P3V_49OHM | \\\n+\t\t\t\tPAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)\n+\n+static iomux_v3_cfg_t const uart1_pads[] = {\n+\tMX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),\n+\tMX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),\n+};\n+\n+PADS_SET(uart1_pads)\n+\n+#ifdef CONFIG_SPI\n+\n+#define SPI_PAD_CTRL\t(PAD_CTL_HYS | PAD_CTL_SRE_SLOW | \\\n+\t\t\tPAD_CTL_DSE_3P3V_32OHM)\n+\n+#define GPIO_PAD_CTRL\t(PAD_CTL_PUS_PU5KOHM | PAD_CTL_PUE | \\\n+\t\t\tPAD_CTL_SRE_SLOW)\n+\n+static iomux_v3_cfg_t const espi1_pads[] = {\n+\tMX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),\n+\tMX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),\n+\tMX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),\n+\tMX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL),\n+};\n+\n+PADS_SET(espi1_pads)\n+\n+#endif /* CONFIG_SPI */\n+\n+#ifndef CONFIG_SPL_BUILD\n+\n+#ifdef CONFIG_FSL_ESDHC\n+\n+static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {\n+\tMX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\tMX7D_PAD_SD3_STROBE__SD3_STROBE\t | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+\n+\tMX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n+};\n+\n+PADS_SET(usdhc3_emmc_pads)\n+\n+#endif /* CONFIG_FSL_ESDHC */\n+\n+#ifdef CONFIG_FEC_MXC\n+\n+#define ENET_PAD_CTRL\t\t(PAD_CTL_PUS_PD100KOHM | PAD_CTL_DSE_3P3V_49OHM)\n+#define ENET_PAD_CTRL_MII\t(PAD_CTL_PUS_PU5KOHM)\n+\n+static iomux_v3_cfg_t const phy1_rst_pads[] = {\n+\t/* PHY1 RST */\n+\tMX7D_PAD_GPIO1_IO04__GPIO1_IO4\t| MUX_PAD_CTRL(GPIO_PAD_CTRL),\n+};\n+\n+PADS_SET(phy1_rst_pads)\n+\n+static iomux_v3_cfg_t const fec1_pads[] = {\n+\tMX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL |\n+\tMUX_PAD_CTRL(ENET_PAD_CTRL),\n+\tMX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n+\tMX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n+\tMX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n+\tMX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n+\tMX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),\n+\tMX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL |\n+\tMUX_PAD_CTRL(ENET_PAD_CTRL),\n+\tMX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n+\tMX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n+\tMX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n+\tMX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n+\tMX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),\n+\tMX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),\n+\tMX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),\n+};\n+\n+PADS_SET(fec1_pads)\n+\n+#endif /* CONFIG_FEC_MXC */\n+\n+static iomux_v3_cfg_t const usb_otg1_pads[] = {\n+\tMX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),\n+};\n+\n+PADS_SET(usb_otg1_pads)\n+\n+static iomux_v3_cfg_t const wdog_pads[] = {\n+\tMX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),\n+};\n+\n+PADS_SET(wdog_pads)\n+\n+#endif /* !CONFIG_SPL_BUILD */\ndiff --git a/board/compulab/cl-som-imx7/spl.c b/board/compulab/cl-som-imx7/spl.c\nnew file mode 100644\nindex 0000000..3b013c0\n--- /dev/null\n+++ b/board/compulab/cl-som-imx7/spl.c\n@@ -0,0 +1,211 @@\n+/*\n+ * SPL board functions for CompuLab CL-SOM-iMX7 module\n+ *\n+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com\n+ *\n+ * Author: Uri Mashiach \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \"common.h\"\n+\n+#ifdef CONFIG_FSL_ESDHC\n+\n+static struct fsl_esdhc_cfg cl_som_imx7_spl_usdhc_cfg = {\n+\tUSDHC1_BASE_ADDR, 0, 4};\n+\n+int board_mmc_init(bd_t *bis)\n+{\n+\tcl_som_imx7_usdhc1_pads_set();\n+\tcl_som_imx7_spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);\n+\treturn fsl_esdhc_initialize(bis, &cl_som_imx7_spl_usdhc_cfg);\n+}\n+#endif /* CONFIG_FSL_ESDHC */\n+\n+static iomux_v3_cfg_t const led_pads[] = {\n+\tMX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 | MUX_PAD_CTRL(PAD_CTL_PUS_PU5KOHM |\n+\t\tPAD_CTL_PUE | PAD_CTL_SRE_SLOW)\n+};\n+\n+static struct ddrc cl_som_imx7_spl_ddrc_regs_val = {\n+\t.init1\t\t= 0x00690000,\n+\t.init0\t\t= 0x00020083,\n+\t.init3\t\t= 0x09300004,\n+\t.init4\t\t= 0x04080000,\n+\t.init5\t\t= 0x00100004,\n+\t.rankctl\t= 0x0000033F,\n+\t.dramtmg1\t= 0x0007020E,\n+\t.dramtmg2\t= 0x03040407,\n+\t.dramtmg3\t= 0x00002006,\n+\t.dramtmg4\t= 0x04020305,\n+\t.dramtmg5\t= 0x03030202,\n+\t.dramtmg8\t= 0x00000803,\n+\t.zqctl0\t\t= 0x00810021,\n+\t.dfitmg0\t= 0x02098204,\n+\t.dfitmg1\t= 0x00030303,\n+\t.dfiupd0\t= 0x80400003,\n+\t.dfiupd1\t= 0x00100020,\n+\t.dfiupd2\t= 0x80100004,\n+\t.addrmap4\t= 0x00000F0F,\n+\t.odtcfg\t\t= 0x06000604,\n+\t.odtmap\t\t= 0x00000001,\n+};\n+\n+static struct ddrc_mp cl_som_imx7_spl_ddrc_mp_val = {\n+\t.pctrl_0\t= 0x00000001,\n+};\n+\n+static struct ddr_phy cl_som_imx7_spl_ddr_phy_regs_val = {\n+\t.phy_con0\t= 0x17420F40,\n+\t.phy_con1\t= 0x10210100,\n+\t.phy_con4\t= 0x00060807,\n+\t.mdll_con0\t= 0x1010007E,\n+\t.drvds_con0\t= 0x00000D6E,\n+\t.cmd_sdll_con0\t= 0x00000010,\n+\t.offset_lp_con0\t= 0x0000000F,\n+};\n+\n+struct mx7_calibration cl_som_imx7_spl_calib_param = {\n+\t.num_val\t= 5,\n+\t.values\t\t= {\n+\t\t0x0E407304,\n+\t\t0x0E447304,\n+\t\t0x0E447306,\n+\t\t0x0E447304,\n+\t\t0x0E407304,\n+\t},\n+};\n+\n+static void cl_som_imx7_spl_dram_cfg_size(u32 ram_size)\n+{\n+\tswitch (ram_size) {\n+\tcase SZ_256M:\n+\t\tcl_som_imx7_spl_ddrc_regs_val.mstr\t\t= 0x01041001;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.rfshtmg\t\t= 0x00400046;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.dramtmg0\t\t= 0x090E1109;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap0\t\t= 0x00000014;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap1\t\t= 0x00151515;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap5\t\t= 0x03030303;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap6\t\t= 0x0F0F0303;\n+\t\tcl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0\t= 0x0C0C0C0C;\n+\t\tcl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0\t= 0x04040404;\n+\t\tbreak;\n+\tcase SZ_512M:\n+\t\tcl_som_imx7_spl_ddrc_regs_val.mstr\t\t= 0x01040001;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.rfshtmg\t\t= 0x00400046;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.dramtmg0\t\t= 0x090E1109;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap0\t\t= 0x00000015;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap1\t\t= 0x00161616;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap5\t\t= 0x04040404;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap6\t\t= 0x0F0F0404;\n+\t\tcl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0\t= 0x0C0C0C0C;\n+\t\tcl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0\t= 0x04040404;\n+\t\tbreak;\n+\tcase SZ_1G:\n+\t\tcl_som_imx7_spl_ddrc_regs_val.mstr\t\t= 0x01040001;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.rfshtmg\t\t= 0x00400046;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.dramtmg0\t\t= 0x090E1109;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap0\t\t= 0x00000016;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap1\t\t= 0x00171717;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap5\t\t= 0x04040404;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap6\t\t= 0x0F040404;\n+\t\tcl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0\t= 0x0A0A0A0A;\n+\t\tcl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0\t= 0x02020202;\n+\t\tbreak;\n+\tcase SZ_2G:\n+\t\tcl_som_imx7_spl_ddrc_regs_val.mstr\t\t= 0x01040001;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.rfshtmg\t\t= 0x0040005E;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.dramtmg0\t\t= 0x090E110A;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap0\t\t= 0x00000018;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap1\t\t= 0x00181818;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap5\t\t= 0x04040404;\n+\t\tcl_som_imx7_spl_ddrc_regs_val.addrmap6\t\t= 0x04040404;\n+\t\tcl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0\t= 0x0A0A0A0A;\n+\t\tcl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0\t= 0x04040404;\n+\t\tbreak;\n+\t}\n+\n+\tmx7_dram_cfg(&cl_som_imx7_spl_ddrc_regs_val,\n+\t\t &cl_som_imx7_spl_ddrc_mp_val,\n+\t\t &cl_som_imx7_spl_ddr_phy_regs_val,\n+\t\t &cl_som_imx7_spl_calib_param);\n+}\n+\n+static void cl_som_imx7_spl_dram_cfg(void)\n+{\n+\tulong ram_size_test, ram_size = 0;\n+\n+\tfor (ram_size = SZ_2G; ram_size >= SZ_256M; ram_size >>= 1) {\n+\t\tcl_som_imx7_spl_dram_cfg_size(ram_size);\n+\t\tram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);\n+\t\tif (ram_size_test == ram_size)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (ram_size < SZ_256M) {\n+\t\tputs(\"!!!ERROR!!! DRAM detection failed!!!\\n\");\n+\t\thang();\n+\t}\n+}\n+\n+#ifdef CONFIG_SPL_SPI_SUPPORT\n+\n+static void cl_som_imx7_spl_spi_init(void)\n+{\n+\tcl_som_imx7_espi1_pads_set();\n+}\n+#else /* !CONFIG_SPL_SPI_SUPPORT */\n+static void cl_som_imx7_spl_spi_init(void) {}\n+#endif /* CONFIG_SPL_SPI_SUPPORT */\n+\n+void board_init_f(ulong dummy)\n+{\n+\timx_iomux_v3_setup_multiple_pads(led_pads, 1);\n+\t/* setup AIPS and disable watchdog */\n+\tarch_cpu_init();\n+\t/* setup GP timer */\n+\ttimer_init();\n+\tcl_som_imx7_spl_spi_init();\n+\tcl_som_imx7_uart1_pads_set();\n+\t/* UART clocks enabled and gd valid - init serial console */\n+\tpreloader_console_init();\n+\t/* DRAM detection */\n+\tcl_som_imx7_spl_dram_cfg();\n+\t/* Clear the BSS. */\n+\tmemset(__bss_start, 0, __bss_end - __bss_start);\n+\t/* load/boot image from boot device */\n+\tboard_init_r(NULL, 0);\n+}\n+\n+void spl_board_init(void)\n+{\n+\tu32 boot_device = spl_boot_device();\n+\n+\tif (boot_device == BOOT_DEVICE_SPI)\n+\t\tputs(\"Booting from SPI flash\\n\");\n+\telse if (boot_device == BOOT_DEVICE_MMC1)\n+\t\tputs(\"Booting from SD card\\n\");\n+\telse\n+\t\tputs(\"Unknown boot device\\n\");\n+}\n+\n+void board_boot_order(u32 *spl_boot_list)\n+{\n+\tspl_boot_list[0] = spl_boot_device();\n+\tswitch (spl_boot_list[0]) {\n+\tcase BOOT_DEVICE_SPI:\n+\t\tspl_boot_list[1] = BOOT_DEVICE_MMC1;\n+\t\tbreak;\n+\tcase BOOT_DEVICE_MMC1:\n+\t\tspl_boot_list[1] = BOOT_DEVICE_SPI;\n+\t\tbreak;\n+\t}\n+}\ndiff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig\nnew file mode 100644\nindex 0000000..6c1d241\n--- /dev/null\n+++ b/configs/cl-som-imx7_defconfig\n@@ -0,0 +1,54 @@\n+CONFIG_ARM=y\n+CONFIG_ARCH_MX7=y\n+CONFIG_SPL_GPIO_SUPPORT=y\n+CONFIG_SPL_LIBCOMMON_SUPPORT=y\n+CONFIG_SPL_LIBGENERIC_SUPPORT=y\n+CONFIG_TARGET_CL_SOM_IMX7=y\n+CONFIG_SPL_MMC_SUPPORT=y\n+CONFIG_SPL_SERIAL_SUPPORT=y\n+CONFIG_SPL_SPI_FLASH_SUPPORT=y\n+CONFIG_SPL_SPI_SUPPORT=y\n+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y\n+CONFIG_IMX_RDC=y\n+CONFIG_IMX_BOOTAUX=y\n+CONFIG_SYS_EXTRA_OPTIONS=\"IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg\"\n+CONFIG_SPI_BOOT=y\n+CONFIG_BOOTDELAY=3\n+CONFIG_SPL=y\n+CONFIG_SPL_BOARD_INIT=y\n+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y\n+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80\n+CONFIG_SPL_I2C_SUPPORT=y\n+CONFIG_HUSH_PARSER=y\n+CONFIG_SYS_PROMPT=\"CL-SOM-iMX7 # \"\n+CONFIG_CMD_BOOTZ=y\n+# CONFIG_CMD_IMI is not set\n+# CONFIG_CMD_IMLS is not set\n+# CONFIG_CMD_XIMG is not set\n+# CONFIG_CMD_EXPORTENV is not set\n+# CONFIG_CMD_IMPORTENV is not set\n+CONFIG_CMD_GREPENV=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_SF=y\n+CONFIG_CMD_I2C=y\n+CONFIG_CMD_USB=y\n+CONFIG_CMD_GPIO=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_MII=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_CACHE=y\n+CONFIG_CMD_EXT2=y\n+CONFIG_CMD_EXT4=y\n+CONFIG_CMD_EXT4_WRITE=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_FS_GENERIC=y\n+CONFIG_ENV_IS_IN_SPI_FLASH=y\n+CONFIG_SPI_FLASH=y\n+CONFIG_SPI_FLASH_STMICRO=y\n+CONFIG_USB=y\n+CONFIG_USB_EHCI_HCD=y\n+CONFIG_MXC_USB_OTG_HACTIVE=y\n+CONFIG_USB_STORAGE=y\n+CONFIG_USB_GADGET=y\n+CONFIG_CI_UDC=y\n+CONFIG_OF_LIBFDT=y\ndiff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h\nnew file mode 100644\nindex 0000000..14c4712\n--- /dev/null\n+++ b/include/configs/cl-som-imx7.h\n@@ -0,0 +1,192 @@\n+/*\n+ * Copyright (C) 2015 CompuLab, Ltd.\n+ *\n+ * Configuration settings for the CompuLab CL-SOM-iMX7 System-on-Module.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CL_SOM_IMX7_CONFIG_H\n+#define __CL_SOM_IMX7_CONFIG_H\n+\n+#include \"mx7_common.h\"\n+\n+#define CONFIG_DBG_MONITOR\n+\n+#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR\n+\n+/* Size of malloc() pool */\n+#define CONFIG_SYS_MALLOC_LEN\t\t(32 * SZ_1M)\n+\n+#define CONFIG_BOARD_LATE_INIT\n+\n+/* Uncomment to enable secure boot support */\n+/* #define CONFIG_SECURE_BOOT */\n+#define CONFIG_CSF_SIZE\t\t\t0x4000\n+\n+/* Network */\n+#define CONFIG_FEC_MXC\n+#define CONFIG_MII\n+#define CONFIG_FEC_XCV_TYPE RGMII\n+#define CONFIG_ETHPRIME \"FEC\"\n+#define CONFIG_FEC_MXC_PHYADDR 0\n+\n+#define CONFIG_PHYLIB\n+#define CONFIG_PHY_ATHEROS\n+/* ENET1 */\n+#define IMX_FEC_BASE\t\t\tENET_IPS_BASE_ADDR\n+\n+/* PMIC */\n+#define CONFIG_POWER\n+#define CONFIG_POWER_I2C\n+#define CONFIG_POWER_PFUZE3000\n+#define CONFIG_POWER_PFUZE3000_I2C_ADDR\t0x08\n+\n+#undef CONFIG_BOOTM_NETBSD\n+#undef CONFIG_BOOTM_PLAN9\n+#undef CONFIG_BOOTM_RTEMS\n+\n+/* I2C configs */\n+#define CONFIG_SYS_I2C\n+#define CONFIG_SYS_I2C_MXC\n+#define CONFIG_SYS_I2C_MXC_I2C2\t\t/* Enable I2C bus 2 */\n+#define CONFIG_SYS_I2C_SPEED\t\t100000\n+#define SYS_I2C_BUS_SOM\t\t\t0\n+\n+#define CONFIG_SYS_I2C_EEPROM_ADDR\t0x50\n+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN\t1\n+#define CONFIG_SYS_I2C_EEPROM_BUS\tSYS_I2C_BUS_SOM\n+\n+#define CONFIG_PCA953X\n+#define CONFIG_CMD_PCA953X\n+#define CONFIG_SYS_I2C_PCA953X_ADDR\t0x20\n+#define CONFIG_SYS_I2C_PCA953X_WIDTH\t{ {0x20, 16} }\n+\n+#undef CONFIG_SYS_AUTOLOAD\n+#undef CONFIG_EXTRA_ENV_SETTINGS\n+#undef CONFIG_BOOTCOMMAND\n+#undef CONFIG_BOOTDELAY\n+\n+#define CONFIG_BOOTDELAY\t\t3\n+#define CONFIG_SYS_AUTOLOAD\t\t\"no\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS \\\n+\t\"autoload=off\\0\" \\\n+\t\"script=boot.scr\\0\" \\\n+\t\"loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\\0\" \\\n+\t\"loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\\0\" \\\n+\t\"loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${fdtfile};\\0\" \\\n+\t\"bootscript=echo Running bootscript from ${storagetype} ...; source ${loadaddr};\\0\" \\\n+\t\"storagebootcmd=echo Booting from ${storagetype} ...; run ${storagetype}args; run doboot;\\0\" \\\n+\t\"kernel=zImage\\0\" \\\n+\t\"console=ttymxc0\\0\" \\\n+\t\"fdt_high=0xffffffff\\0\" \\\n+\t\"initrd_high=0xffffffff\\0\" \\\n+\t\"fdtfile=imx7d-sbc-imx7.dtb\\0\" \\\n+\t\"fdtaddr=0x83000000\\0\" \\\n+\t\"mmcdev_def=\"__stringify(CONFIG_SYS_MMC_DEV)\"\\0\" \\\n+\t\"usbdev_def=\"__stringify(CONFIG_SYS_USB_DEV)\"\\0\" \\\n+\t\"mmcpart=\" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) \"\\0\" \\\n+\t\"usbpart=\" __stringify(CONFIG_SYS_USB_IMG_LOAD_PART) \"\\0\" \\\n+\t\"doboot=bootz ${loadaddr} - ${fdtaddr}\\0\" \\\n+\t\"mmc_config=mmc dev ${mmcdev}; mmc rescan\\0\" \\\n+\t\"mmcargs=setenv bootargs console=${console},${baudrate} \" \\\n+\t\t\"root=/dev/mmcblk${mmcblk}p2 rootwait rw\\0\" \\\n+\t\"mmcbootscript=\" \\\n+\t\t\"if run mmc_config; then \" \\\n+\t\t\t\"setenv storagetype mmc;\" \\\n+\t\t\t\"setenv storagedev ${mmcdev}:${mmcpart};\" \\\n+\t\t\t\"if run loadscript; then \" \\\n+\t\t\t\t\"run bootscript; \" \\\n+\t\t\t\"fi; \" \\\n+\t\t\"fi;\\0\" \\\n+\t\"mmcboot=\" \\\n+\t\t\"if run mmc_config; then \" \\\n+\t\t\t\"setenv storagetype mmc;\" \\\n+\t\t\t\"setenv storagedev ${mmcdev}:${mmcpart};\" \\\n+\t\t\t\"if run loadkernel; then \" \\\n+\t\t\t\t\"if run loadfdt; then \" \\\n+\t\t\t\t\t\"run storagebootcmd;\" \\\n+\t\t\t\t\"fi; \" \\\n+\t\t\t\"fi; \" \\\n+\t\t\"fi;\\0\" \\\n+\t\"sdbootscript=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; \" \\\n+\t\t\"run mmcbootscript\\0\" \\\n+\t\"usbbootscript=setenv usbdev ${usbdev_def}; \" \\\n+\t\t\"setenv storagetype usb;\" \\\n+\t\t\"setenv storagedev ${usbdev}:${usbpart};\" \\\n+\t\t\"if run loadscript; then \" \\\n+\t\t\t\"run bootscript; \" \\\n+\t\t\"fi; \" \\\n+\t\"sdboot=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; run mmcboot\\0\" \\\n+\t\"emmcbootscript=setenv mmcdev 1; setenv mmcblk 2; run mmcbootscript\\0\" \\\n+\t\"emmcboot=setenv mmcdev 1; setenv mmcblk 2; run mmcboot\\0\" \\\n+\n+#define CONFIG_BOOTCOMMAND \\\n+\t\"echo SD boot attempt ...; run sdbootscript; run sdboot; \" \\\n+\t\"echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; \" \\\n+\t\"echo USB boot attempt ...; run usbbootscript; \"\n+\n+#define CONFIG_SYS_MEMTEST_START\t0x80000000\n+#define CONFIG_SYS_MEMTEST_END\t\t(CONFIG_SYS_MEMTEST_START + 0x20000000)\n+\n+#define CONFIG_SYS_LOAD_ADDR\t\tCONFIG_LOADADDR\n+#define CONFIG_SYS_HZ\t\t\t1000\n+\n+/* Physical Memory Map */\n+#define CONFIG_NR_DRAM_BANKS\t\t1\n+#define PHYS_SDRAM\t\t\tMMDC0_ARB_BASE_ADDR\n+\n+#define CONFIG_SYS_SDRAM_BASE\t\tPHYS_SDRAM\n+#define CONFIG_SYS_INIT_RAM_ADDR\tIRAM_BASE_ADDR\n+#define CONFIG_SYS_INIT_RAM_SIZE\tIRAM_SIZE\n+\n+#define CONFIG_SYS_INIT_SP_OFFSET \\\n+\t(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)\n+#define CONFIG_SYS_INIT_SP_ADDR \\\n+\t(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)\n+\n+/* SPI Flash support */\n+#define CONFIG_SPI\n+#define CONFIG_MXC_SPI\n+#define CONFIG_SF_DEFAULT_BUS\t\t0\n+#define CONFIG_SF_DEFAULT_CS\t\t0\n+#define CONFIG_SF_DEFAULT_SPEED\t\t20000000\n+#define CONFIG_SF_DEFAULT_MODE\t\t(SPI_MODE_0)\n+\n+/* FLASH and environment organization */\n+#define CONFIG_ENV_SIZE\t\t\tSZ_8K\n+#define CONFIG_ENV_OFFSET\t\t(768 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(64 * 1024)\n+#define CONFIG_ENV_SPI_BUS\t\tCONFIG_SF_DEFAULT_BUS\n+#define CONFIG_ENV_SPI_CS\t\tCONFIG_SF_DEFAULT_CS\n+#define CONFIG_ENV_SPI_MODE\t\tCONFIG_SF_DEFAULT_MODE\n+#define CONFIG_ENV_SPI_MAX_HZ\t\tCONFIG_SF_DEFAULT_SPEED\n+\n+/* MMC Config*/\n+#define CONFIG_FSL_USDHC\n+#ifdef CONFIG_FSL_USDHC\n+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR\n+\n+#define CONFIG_SYS_FSL_USDHC_NUM\t2\n+#define CONFIG_MMCROOT\t\t\t\"/dev/mmcblk0p2\" /* USDHC1 */\n+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */\n+#endif\n+\n+/* USB Configs */\n+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET\n+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)\n+#define CONFIG_MXC_USB_FLAGS 0\n+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2\n+\n+/* Uncomment to enable iMX thermal driver support */\n+/*#define CONFIG_IMX_THERMAL*/\n+\n+/* SPL */\n+#include \"imx7_spl.h\"\n+#ifdef CONFIG_SPL_BUILD\n+#define CONFIG_SPL_SPI_LOAD\n+#define CONFIG_SYS_SPI_U_BOOT_OFFS\t(64 * 1024)\n+#endif /* CONFIG_SPL_BUILD */\n+\n+#endif\t/* __CONFIG_H */\n","prefixes":["U-Boot","4/4"]}