{"id":817657,"url":"http://patchwork.ozlabs.org/api/patches/817657/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170922171323.10348-5-f4bug@amsat.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170922171323.10348-5-f4bug@amsat.org>","list_archive_url":null,"date":"2017-09-22T17:13:20","name":"[v5,4/7] hw/mdio: Mask out read-only bits.","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b08ee0523af56592796c3089f2831e852471f46f","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/?format=json","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170922171323.10348-5-f4bug@amsat.org/mbox/","series":[{"id":4680,"url":"http://patchwork.ozlabs.org/api/series/4680/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4680","date":"2017-09-22T17:13:16","name":"Generalize MDIO framework","version":5,"mbox":"http://patchwork.ozlabs.org/series/4680/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/817657/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/817657/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::241","Subject":"[Qemu-devel] [PATCH v5 4/7] hw/mdio: Mask out read-only bits.","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-devel@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?=\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Grant Likely \n\nThe RST and ANEG_RST bits are commands, not settings. An operating\nsystem will get confused (or at least u-boot does) if those bits remain\nset after writing to them. Therefore, mask them out on write.\n\nSimilarly, no bits in the ID1, ID2, and remote capability registers are\nwriteable; so mask them out also.\n\nSigned-off-by: Grant Likely \nSigned-off-by: Philippe Mathieu-Daudé \n[PMD: just rebased]\n---\n include/hw/net/mdio.h | 1 +\n hw/net/mdio.c | 16 ++++++++++++----\n 2 files changed, 13 insertions(+), 4 deletions(-)","diff":"diff --git a/include/hw/net/mdio.h b/include/hw/net/mdio.h\nindex b3b4f497c0..ed1879a728 100644\n--- a/include/hw/net/mdio.h\n+++ b/include/hw/net/mdio.h\n@@ -53,6 +53,7 @@\n \n struct qemu_phy {\n uint32_t regs[NUM_PHY_REGS];\n+ const uint16_t *regs_readonly_mask; /* 0=writable, 1=read-only */\n \n int link;\n \ndiff --git a/hw/net/mdio.c b/hw/net/mdio.c\nindex 33bfbb4623..89a6a3a590 100644\n--- a/hw/net/mdio.c\n+++ b/hw/net/mdio.c\n@@ -109,17 +109,24 @@ static unsigned int mdio_phy_read(struct qemu_phy *phy, unsigned int req)\n \n static void mdio_phy_write(struct qemu_phy *phy, unsigned int req, unsigned int data)\n {\n- int regnum;\n+ int regnum = req & 0x1f;\n+ uint16_t mask = phy->regs_readonly_mask[regnum];\n \n- regnum = req & 0x1f;\n- D(printf(\"%s reg[%d] = %x\\n\", __func__, regnum, data));\n+ D(printf(\"%s reg[%d] = %x; mask=%x\\n\", __func__, regnum, data, mask));\n switch (regnum) {\n default:\n- phy->regs[regnum] = data;\n+ phy->regs[regnum] = (phy->regs[regnum] & mask) | (data & ~mask);\n break;\n }\n }\n \n+static const uint16_t default_readonly_mask[32] = {\n+ [PHY_CTRL] = PHY_CTRL_RST | PHY_CTRL_ANEG_RST,\n+ [PHY_ID1] = 0xffff,\n+ [PHY_ID2] = 0xffff,\n+ [PHY_LP_ABILITY] = 0xffff,\n+};\n+\n void mdio_phy_init(struct qemu_phy *phy, uint16_t id1, uint16_t id2)\n {\n phy->regs[PHY_CTRL] = 0x3100;\n@@ -128,6 +135,7 @@ void mdio_phy_init(struct qemu_phy *phy, uint16_t id1, uint16_t id2)\n phy->regs[PHY_ID2] = id2;\n /* Autonegotiation advertisement reg. */\n phy->regs[PHY_AUTONEG_ADV] = 0x01e1;\n+ phy->regs_readonly_mask = default_readonly_mask;\n phy->link = 1;\n \n phy->read = mdio_phy_read;\n","prefixes":["v5","4/7"]}