{"id":817655,"url":"http://patchwork.ozlabs.org/api/patches/817655/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170922171323.10348-3-f4bug@amsat.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170922171323.10348-3-f4bug@amsat.org>","list_archive_url":null,"date":"2017-09-22T17:13:18","name":"[v5,2/7] hw/mdio: Add PHY register definition","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1a7027d33fb4d1d88438f2530d88c2b37cff941a","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/?format=json","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170922171323.10348-3-f4bug@amsat.org/mbox/","series":[{"id":4680,"url":"http://patchwork.ozlabs.org/api/series/4680/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4680","date":"2017-09-22T17:13:16","name":"Generalize MDIO framework","version":5,"mbox":"http://patchwork.ozlabs.org/series/4680/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/817655/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/817655/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::244","Subject":"[Qemu-devel] [PATCH v5 2/7] hw/mdio: Add PHY register definition","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-devel@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?=\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Grant Likely \n\nTrivial patch to add #defines for defined PHY register address and bit fields\n\nSigned-off-by: Grant Likely \nSigned-off-by: Philippe Mathieu-Daudé \n---\n include/hw/net/mdio.h | 24 ++++++++++++++++++++++--\n hw/net/mdio.c | 8 ++++----\n 2 files changed, 26 insertions(+), 6 deletions(-)","diff":"diff --git a/include/hw/net/mdio.h b/include/hw/net/mdio.h\nindex ac36aed3c3..7ffa4389b9 100644\n--- a/include/hw/net/mdio.h\n+++ b/include/hw/net/mdio.h\n@@ -25,14 +25,34 @@\n * THE SOFTWARE.\n */\n \n-/* PHY Advertisement control register */\n+/* PHY MII Register/Bit Definitions */\n+/* PHY Registers defined by IEEE */\n+#define PHY_CTRL 0x00 /* Control Register */\n+#define PHY_STATUS 0x01 /* Status Regiser */\n+#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */\n+#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */\n+#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */\n+#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */\n+#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */\n+#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */\n+#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */\n+#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */\n+#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */\n+#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */\n+\n+#define NUM_PHY_REGS 0x20 /* 5 bit address bus (0-0x1F) */\n+\n+#define PHY_CTRL_RST 0x8000 /* PHY reset command */\n+#define PHY_CTRL_ANEG_RST 0x0200 /* Autonegotiation reset command */\n+\n+/* PHY Advertisement control and remote capability registers (same bitfields) */\n #define PHY_ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */\n #define PHY_ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */\n #define PHY_ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */\n #define PHY_ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */\n \n struct qemu_phy {\n- uint32_t regs[32];\n+ uint32_t regs[NUM_PHY_REGS];\n \n int link;\n \ndiff --git a/hw/net/mdio.c b/hw/net/mdio.c\nindex 3763fcc8af..3d70d99077 100644\n--- a/hw/net/mdio.c\n+++ b/hw/net/mdio.c\n@@ -122,12 +122,12 @@ static void tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data)\n \n void tdk_init(struct qemu_phy *phy)\n {\n- phy->regs[0] = 0x3100;\n+ phy->regs[PHY_CTRL] = 0x3100;\n /* PHY Id. */\n- phy->regs[2] = 0x0300;\n- phy->regs[3] = 0xe400;\n+ phy->regs[PHY_ID1] = 0x0300;\n+ phy->regs[PHY_ID2] = 0xe400;\n /* Autonegotiation advertisement reg. */\n- phy->regs[4] = 0x01e1;\n+ phy->regs[PHY_AUTONEG_ADV] = 0x01e1;\n phy->link = 1;\n \n phy->read = tdk_read;\n","prefixes":["v5","2/7"]}