{"id":817577,"url":"http://patchwork.ozlabs.org/api/patches/817577/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-21-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506092407-26985-21-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-22T15:00:07","name":"[20/20] nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c6c0b52aa301d32887216eb7ae705354aec81942","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-21-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":4650,"url":"http://patchwork.ozlabs.org/api/series/4650/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4650","date":"2017-09-22T14:59:47","name":"ARM v8M: exception entry, exit and security","version":1,"mbox":"http://patchwork.ozlabs.org/series/4650/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/817577/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/817577/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzH8q2WzVz9sNw\n\tfor ;\n\tSat, 23 Sep 2017 01:15:07 +1000 (AEST)","from localhost ([::1]:59406 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dvPfV-0004Tm-Ec\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 11:15:05 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:47317)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dvPQl-000897-IC\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:52 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dvPQk-0004Lv-Qs\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:51 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37588)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dvPQf-0004EW-G1; Fri, 22 Sep 2017 10:59:45 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from )\n\tid 1dvPQd-0007H9-Mw; Fri, 22 Sep 2017 15:59:43 +0100"],"From":"Peter Maydell ","To":"qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Date":"Fri, 22 Sep 2017 16:00:07 +0100","Message-Id":"<1506092407-26985-21-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PATCH 20/20] nvic: Add missing code for writing\n\tSHCSR.HARDFAULTPENDED bit","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"When we added support for the new SHCSR bits in v8M in commit\n437d59c17e9 the code to support writing to the new HARDFAULTPENDED\nbit was accidentally only added for non-secure writes; the\nsecure banked version of the bit should also be writable.\n\nSigned-off-by: Peter Maydell \n---\n hw/intc/armv7m_nvic.c | 1 +\n 1 file changed, 1 insertion(+)","diff":"diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex bd1d5d3..22d5e6e 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -1230,6 +1230,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,\n s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;\n s->sec_vectors[ARMV7M_EXCP_USAGE].enabled =\n (value & (1 << 18)) != 0;\n+ s->sec_vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0;\n /* SecureFault not banked, but RAZ/WI to NS */\n s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0;\n s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0;\n","prefixes":["20/20"]}