{"id":817572,"url":"http://patchwork.ozlabs.org/api/patches/817572/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-10-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506092407-26985-10-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-22T14:59:56","name":"[09/20] target/arm: Add new-in-v8M SFSR and SFAR","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6a60bd345716d88324c7b1361143a9abe76cc92d","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-10-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":4650,"url":"http://patchwork.ozlabs.org/api/series/4650/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4650","date":"2017-09-22T14:59:47","name":"ARM v8M: exception entry, exit and security","version":1,"mbox":"http://patchwork.ozlabs.org/series/4650/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/817572/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/817572/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzH4W1V20z9sNw\n\tfor ;\n\tSat, 23 Sep 2017 01:11:23 +1000 (AEST)","from localhost ([::1]:59380 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dvPbt-0000wF-0T\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 11:11:21 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:47100)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dvPQc-00080z-7f\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:43 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dvPQb-0004Ax-8U\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:42 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37556)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dvPQY-00043B-8m; Fri, 22 Sep 2017 10:59:38 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from )\n\tid 1dvPQV-0007Bi-WB; Fri, 22 Sep 2017 15:59:36 +0100"],"From":"Peter Maydell ","To":"qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Date":"Fri, 22 Sep 2017 15:59:56 +0100","Message-Id":"<1506092407-26985-10-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PATCH 09/20] target/arm: Add new-in-v8M SFSR and SFAR","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Add the new M profile Secure Fault Status Register\nand Secure Fault Address Register.\n\nSigned-off-by: Peter Maydell \n---\n target/arm/cpu.h | 12 ++++++++++++\n hw/intc/armv7m_nvic.c | 34 ++++++++++++++++++++++++++++++++++\n target/arm/machine.c | 2 ++\n 3 files changed, 48 insertions(+)","diff":"diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex ad6eff4..9e3a16d 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -443,8 +443,10 @@ typedef struct CPUARMState {\n uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */\n uint32_t hfsr; /* HardFault Status */\n uint32_t dfsr; /* Debug Fault Status Register */\n+ uint32_t sfsr; /* Secure Fault Status Register */\n uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */\n uint32_t bfar; /* BusFault Address */\n+ uint32_t sfar; /* Secure Fault Address Register */\n unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */\n int exception;\n uint32_t primask[M_REG_NUM_BANKS];\n@@ -1260,6 +1262,16 @@ FIELD(V7M_DFSR, DWTTRAP, 2, 1)\n FIELD(V7M_DFSR, VCATCH, 3, 1)\n FIELD(V7M_DFSR, EXTERNAL, 4, 1)\n \n+/* V7M SFSR bits */\n+FIELD(V7M_SFSR, INVEP, 0, 1)\n+FIELD(V7M_SFSR, INVIS, 1, 1)\n+FIELD(V7M_SFSR, INVER, 2, 1)\n+FIELD(V7M_SFSR, AUVIOL, 3, 1)\n+FIELD(V7M_SFSR, INVTRAN, 4, 1)\n+FIELD(V7M_SFSR, LSPERR, 5, 1)\n+FIELD(V7M_SFSR, SFARVALID, 6, 1)\n+FIELD(V7M_SFSR, LSERR, 7, 1)\n+\n /* v7M MPU_CTRL bits */\n FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)\n FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)\ndiff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex a1041c2..deea637 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -1017,6 +1017,22 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)\n goto bad_offset;\n }\n return cpu->env.pmsav8.mair1[attrs.secure];\n+ case 0xde4: /* SFSR */\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ if (!attrs.secure) {\n+ return 0;\n+ }\n+ return cpu->env.v7m.sfsr;\n+ case 0xde8: /* SFAR */\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ if (!attrs.secure) {\n+ return 0;\n+ }\n+ return cpu->env.v7m.sfar;\n default:\n bad_offset:\n qemu_log_mask(LOG_GUEST_ERROR, \"NVIC: Bad read offset 0x%x\\n\", offset);\n@@ -1368,6 +1384,24 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,\n * only affect cacheability, and we don't implement caching.\n */\n break;\n+ case 0xde4: /* SFSR */\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ if (!attrs.secure) {\n+ return;\n+ }\n+ cpu->env.v7m.sfsr &= ~value; /* W1C */\n+ break;\n+ case 0xde8: /* SFAR */\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ if (!attrs.secure) {\n+ return;\n+ }\n+ cpu->env.v7m.sfsr = value;\n+ break;\n case 0xf00: /* Software Triggered Interrupt Register */\n {\n int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;\ndiff --git a/target/arm/machine.c b/target/arm/machine.c\nindex e5fe083..d4b3baf 100644\n--- a/target/arm/machine.c\n+++ b/target/arm/machine.c\n@@ -276,6 +276,8 @@ static const VMStateDescription vmstate_m_security = {\n VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU),\n VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU),\n VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU),\n+ VMSTATE_UINT32(env.v7m.sfsr, ARMCPU),\n+ VMSTATE_UINT32(env.v7m.sfar, ARMCPU),\n VMSTATE_END_OF_LIST()\n }\n };\n","prefixes":["09/20"]}