{"id":817570,"url":"http://patchwork.ozlabs.org/api/patches/817570/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-11-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506092407-26985-11-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-22T14:59:57","name":"[10/20] target/arm: Update excret sanity checks for v8M","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"811b54a87823b9ae2394d1befd9119360ffd3ae6","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-11-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":4650,"url":"http://patchwork.ozlabs.org/api/series/4650/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4650","date":"2017-09-22T14:59:47","name":"ARM v8M: exception entry, exit and security","version":1,"mbox":"http://patchwork.ozlabs.org/series/4650/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/817570/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/817570/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzH2Q1LYJz9s8J\n\tfor ;\n\tSat, 23 Sep 2017 01:09:34 +1000 (AEST)","from localhost ([::1]:59362 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dvPa8-0007o2-7k\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 11:09:32 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:47087)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dvPQb-00080T-RF\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:43 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dvPQa-0004AA-NB\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:41 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37562)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dvPQX-00044o-Pj; Fri, 22 Sep 2017 10:59:37 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from )\n\tid 1dvPQW-0007CA-L7; Fri, 22 Sep 2017 15:59:36 +0100"],"From":"Peter Maydell ","To":"qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Date":"Fri, 22 Sep 2017 15:59:57 +0100","Message-Id":"<1506092407-26985-11-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PATCH 10/20] target/arm: Update excret sanity checks\n\tfor v8M","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"In v8M, more bits are defined in the exception-return magic\nvalues; update the code that checks these so we accept\nthe v8M values when the CPU permits them.\n\nSigned-off-by: Peter Maydell \n---\n target/arm/helper.c | 73 ++++++++++++++++++++++++++++++++++++++++++-----------\n 1 file changed, 58 insertions(+), 15 deletions(-)","diff":"diff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 59a07d2..da3a36e 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6275,8 +6275,9 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n uint32_t excret;\n uint32_t xpsr;\n bool ufault = false;\n- bool return_to_sp_process = false;\n- bool return_to_handler = false;\n+ bool sfault = false;\n+ bool return_to_sp_process;\n+ bool return_to_handler;\n bool rettobase = false;\n bool exc_secure = false;\n bool return_to_secure;\n@@ -6310,6 +6311,19 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n excret);\n }\n \n+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {\n+ /* EXC_RETURN.ES validation check (R_SMFL). We must do this before\n+ * we pick which FAULTMASK to clear.\n+ */\n+ if (!env->v7m.secure &&\n+ ((excret & R_V7M_EXCRET_ES_MASK) ||\n+ !(excret & R_V7M_EXCRET_DCRS_MASK))) {\n+ sfault = 1;\n+ /* For all other purposes, treat ES as 0 (R_HXSR) */\n+ excret &= ~R_V7M_EXCRET_ES_MASK;\n+ }\n+ }\n+\n if (env->v7m.exception != ARMV7M_EXCP_NMI) {\n /* Auto-clear FAULTMASK on return from other than NMI.\n * If the security extension is implemented then this only\n@@ -6347,24 +6361,53 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n g_assert_not_reached();\n }\n \n+ return_to_handler = !(excret & R_V7M_EXCRET_MODE_MASK);\n+ return_to_sp_process = excret & R_V7M_EXCRET_SPSEL_MASK;\n return_to_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&\n (excret & R_V7M_EXCRET_S_MASK);\n \n- switch (excret & 0xf) {\n- case 1: /* Return to Handler */\n- return_to_handler = true;\n- break;\n- case 13: /* Return to Thread using Process stack */\n- return_to_sp_process = true;\n- /* fall through */\n- case 9: /* Return to Thread using Main stack */\n- if (!rettobase &&\n- !(env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_NONBASETHRDENA_MASK)) {\n+ if (arm_feature(env, ARM_FEATURE_V8)) {\n+ if (!arm_feature(env, ARM_FEATURE_M_SECURITY)) {\n+ /* UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);\n+ * we choose to take the UsageFault.\n+ */\n+ if ((excret & R_V7M_EXCRET_S_MASK) ||\n+ (excret & R_V7M_EXCRET_ES_MASK) ||\n+ !(excret & R_V7M_EXCRET_DCRS_MASK)) {\n+ ufault = true;\n+ }\n+ }\n+ if (excret & R_V7M_EXCRET_RES0_MASK) {\n ufault = true;\n }\n- break;\n- default:\n- ufault = true;\n+ } else {\n+ /* For v7M we only recognize certain combinations of the low bits */\n+ switch (excret & 0xf) {\n+ case 1: /* Return to Handler */\n+ break;\n+ case 13: /* Return to Thread using Process stack */\n+ case 9: /* Return to Thread using Main stack */\n+ /* We only need to check NONBASETHRDENA for v7M, because in\n+ * v8M this bit does not exist (it is RES1).\n+ */\n+ if (!rettobase &&\n+ !(env->v7m.ccr[env->v7m.secure] &\n+ R_V7M_CCR_NONBASETHRDENA_MASK)) {\n+ ufault = true;\n+ }\n+ break;\n+ default:\n+ ufault = true;\n+ }\n+ }\n+\n+ if (sfault) {\n+ env->v7m.sfsr |= R_V7M_SFSR_INVER_MASK;\n+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);\n+ v7m_exception_taken(cpu, excret);\n+ qemu_log_mask(CPU_LOG_INT, \"...taking SecureFault on existing \"\n+ \"stackframe: failed EXC_RETURN.ES validity check\\n\");\n+ return;\n }\n \n if (ufault) {\n","prefixes":["10/20"]}