{"id":817569,"url":"http://patchwork.ozlabs.org/api/patches/817569/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-6-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506092407-26985-6-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-22T14:59:52","name":"[05/20] target/arm: Restore SPSEL to correct CONTROL register on exception return","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"bc89fc188aa964d75f45b0ad8ba756e748bb1a4c","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-6-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":4650,"url":"http://patchwork.ozlabs.org/api/series/4650/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4650","date":"2017-09-22T14:59:47","name":"ARM v8M: exception entry, exit and security","version":1,"mbox":"http://patchwork.ozlabs.org/series/4650/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/817569/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/817569/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzH18208Pz9sNw\n\tfor ;\n\tSat, 23 Sep 2017 01:08:28 +1000 (AEST)","from localhost ([::1]:59358 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dvPZ4-0006uM-70\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 11:08:26 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:46993)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dvPQZ-0007x5-3G\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:40 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dvPQY-00045o-1z\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:39 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37534)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dvPQV-0003yz-4n; Fri, 22 Sep 2017 10:59:35 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from )\n\tid 1dvPQT-00079V-6D; Fri, 22 Sep 2017 15:59:33 +0100"],"From":"Peter Maydell ","To":"qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Date":"Fri, 22 Sep 2017 15:59:52 +0100","Message-Id":"<1506092407-26985-6-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PATCH 05/20] target/arm: Restore SPSEL to correct\n\tCONTROL register on exception return","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"On exception return for v8M, the SPSEL bit in the EXC_RETURN magic\nvalue should be restored to the SPSEL bit in the CONTROL register\nbanked specified by the EXC_RETURN.ES bit.\n\nAdd write_v7m_control_spsel_for_secstate() which behaves like\nwrite_v7m_control_spsel() but allows the caller to specify which\nCONTROL bank to use, reimplement write_v7m_control_spsel() in\nterms of it, and use it in exception return.\n\nSigned-off-by: Peter Maydell \n---\n target/arm/helper.c | 40 +++++++++++++++++++++++++++-------------\n 1 file changed, 27 insertions(+), 13 deletions(-)","diff":"diff --git a/target/arm/helper.c b/target/arm/helper.c\nindex a3c63c3..4444d04 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6052,28 +6052,42 @@ static bool v7m_using_psp(CPUARMState *env)\n env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK;\n }\n \n-/* Write to v7M CONTROL.SPSEL bit. This may change the current\n- * stack pointer between Main and Process stack pointers.\n+/* Write to v7M CONTROL.SPSEL bit for the specified security bank.\n+ * This may change the current stack pointer between Main and Process\n+ * stack pointers if it is done for the CONTROL register for the current\n+ * security state.\n */\n-static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel)\n+static void write_v7m_control_spsel_for_secstate(CPUARMState *env,\n+ bool new_spsel,\n+ bool secstate)\n {\n- uint32_t tmp;\n- bool new_is_psp, old_is_psp = v7m_using_psp(env);\n+ bool old_is_psp = v7m_using_psp(env);\n \n- env->v7m.control[env->v7m.secure] =\n- deposit32(env->v7m.control[env->v7m.secure],\n+ env->v7m.control[secstate] =\n+ deposit32(env->v7m.control[secstate],\n R_V7M_CONTROL_SPSEL_SHIFT,\n R_V7M_CONTROL_SPSEL_LENGTH, new_spsel);\n \n- new_is_psp = v7m_using_psp(env);\n+ if (secstate == env->v7m.secure) {\n+ bool new_is_psp = v7m_using_psp(env);\n+ uint32_t tmp;\n \n- if (old_is_psp != new_is_psp) {\n- tmp = env->v7m.other_sp;\n- env->v7m.other_sp = env->regs[13];\n- env->regs[13] = tmp;\n+ if (old_is_psp != new_is_psp) {\n+ tmp = env->v7m.other_sp;\n+ env->v7m.other_sp = env->regs[13];\n+ env->regs[13] = tmp;\n+ }\n }\n }\n \n+/* Write to v7M CONTROL.SPSEL bit. This may change the current\n+ * stack pointer between Main and Process stack pointers.\n+ */\n+static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel)\n+{\n+ write_v7m_control_spsel_for_secstate(env, new_spsel, env->v7m.secure);\n+}\n+\n void write_v7m_exception(CPUARMState *env, uint32_t new_exc)\n {\n /* Write a new value to v7m.exception, thus transitioning into or out\n@@ -6369,7 +6383,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n * Handler mode (and will be until we write the new XPSR.Interrupt\n * field) this does not switch around the current stack pointer.\n */\n- write_v7m_control_spsel(env, return_to_sp_process);\n+ write_v7m_control_spsel_for_secstate(env, return_to_sp_process, exc_secure);\n \n switch_v7m_security_state(env, return_to_secure);\n \n","prefixes":["05/20"]}