{"id":817563,"url":"http://patchwork.ozlabs.org/api/patches/817563/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-16-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506092407-26985-16-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-22T15:00:02","name":"[15/20] target/arm: Fix calculation of secure mm_idx values","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0481f47efdc72d1579f696ceefddbfe2a1d19d36","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-16-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":4650,"url":"http://patchwork.ozlabs.org/api/series/4650/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4650","date":"2017-09-22T14:59:47","name":"ARM v8M: exception entry, exit and security","version":1,"mbox":"http://patchwork.ozlabs.org/series/4650/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/817563/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/817563/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzGwY3ldMz9sNw\n\tfor ;\n\tSat, 23 Sep 2017 01:04:29 +1000 (AEST)","from localhost ([::1]:59336 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dvPVD-0002y0-JE\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 11:04:27 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:47210)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dvPQf-00085G-IK\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:46 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dvPQe-0004Fw-L8\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:45 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37574)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dvPQb-00049B-VF; Fri, 22 Sep 2017 10:59:42 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from )\n\tid 1dvPQa-0007Ef-8q; Fri, 22 Sep 2017 15:59:40 +0100"],"From":"Peter Maydell ","To":"qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Date":"Fri, 22 Sep 2017 16:00:02 +0100","Message-Id":"<1506092407-26985-16-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PATCH 15/20] target/arm: Fix calculation of secure\n\tmm_idx values","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"In cpu_mmu_index() we try to do this:\n if (env->v7m.secure) {\n mmu_idx += ARMMMUIdx_MSUser;\n }\nbut it will give the wrong answer, because ARMMMUIdx_MSUser\nincludes the 0x40 ARM_MMU_IDX_M field, and so does the\nmmu_idx we're adding to, and we'll end up with 0x8n rather\nthan 0x4n. This error is then nullified by the call to\narm_to_core_mmu_idx() which masks out the high part, but\nwe're about to factor out the code that calculates the\nARMMMUIdx values so it can be used without passing it through\narm_to_core_mmu_idx(), so fix this bug first.\n\nSigned-off-by: Peter Maydell \n---\n target/arm/cpu.h | 12 +++++++-----\n 1 file changed, 7 insertions(+), 5 deletions(-)","diff":"diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 441e584..70c1f85 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -2335,14 +2335,16 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)\n int el = arm_current_el(env);\n \n if (arm_feature(env, ARM_FEATURE_M)) {\n- ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv;\n+ ARMMMUIdx mmu_idx;\n \n- if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) {\n- mmu_idx = ARMMMUIdx_MNegPri;\n+ if (el == 0) {\n+ mmu_idx = env->v7m.secure ? ARMMMUIdx_MSUser : ARMMMUIdx_MUser;\n+ } else {\n+ mmu_idx = env->v7m.secure ? ARMMMUIdx_MSPriv : ARMMMUIdx_MPriv;\n }\n \n- if (env->v7m.secure) {\n- mmu_idx += ARMMMUIdx_MSUser;\n+ if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) {\n+ mmu_idx = env->v7m.secure ? ARMMMUIdx_MSNegPri : ARMMMUIdx_MNegPri;\n }\n \n return arm_to_core_mmu_idx(mmu_idx);\n","prefixes":["15/20"]}