{"id":817560,"url":"http://patchwork.ozlabs.org/api/patches/817560/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-5-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506092407-26985-5-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-22T14:59:51","name":"[04/20] target/arm: Restore security state on exception return","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e110ca048c944be989ccf8b1b63ed91b1c66e256","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-5-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":4650,"url":"http://patchwork.ozlabs.org/api/series/4650/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4650","date":"2017-09-22T14:59:47","name":"ARM v8M: exception entry, exit and security","version":1,"mbox":"http://patchwork.ozlabs.org/series/4650/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/817560/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/817560/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzGsj50tmz9sNr\n\tfor ;\n\tSat, 23 Sep 2017 01:02:01 +1000 (AEST)","from localhost ([::1]:59321 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dvPSp-00011q-M1\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 11:01:59 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:46912)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dvPQX-0007uK-2u\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:37 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dvPQV-00043W-UZ\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:37 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37544)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dvPQT-000407-Nl; Fri, 22 Sep 2017 10:59:33 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from )\n\tid 1dvPQS-000790-H2; Fri, 22 Sep 2017 15:59:32 +0100"],"From":"Peter Maydell ","To":"qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Date":"Fri, 22 Sep 2017 15:59:51 +0100","Message-Id":"<1506092407-26985-5-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PATCH 04/20] target/arm: Restore security state on\n\texception return","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Now that we can handle the CONTROL.SPSEL bit not necessarily being\nin sync with the current stack pointer, we can restore the correct\nsecurity state on exception return. This happens before we start\nto read registers off the stack frame, but after we have taken\npossible usage faults for bad exception return magic values and\nupdated CONTROL.SPSEL.\n\nSigned-off-by: Peter Maydell \n---\n target/arm/helper.c | 2 ++\n 1 file changed, 2 insertions(+)","diff":"diff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 509a1aa..a3c63c3 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6371,6 +6371,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n */\n write_v7m_control_spsel(env, return_to_sp_process);\n \n+ switch_v7m_security_state(env, return_to_secure);\n+\n {\n /* The stack pointer we should be reading the exception frame from\n * depends on bits in the magic exception return type value (and\n","prefixes":["04/20"]}