{"id":817559,"url":"http://patchwork.ozlabs.org/api/patches/817559/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-9-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506092407-26985-9-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-22T14:59:55","name":"[08/20] target/arm: Don't warn about exception return with PC low bit set for v8M","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b706a483ef0029f148696b67eb95c75b8fea1411","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-9-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":4650,"url":"http://patchwork.ozlabs.org/api/series/4650/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4650","date":"2017-09-22T14:59:47","name":"ARM v8M: exception entry, exit and security","version":1,"mbox":"http://patchwork.ozlabs.org/series/4650/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/817559/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/817559/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzGrZ399Mz9sPm\n\tfor ;\n\tSat, 23 Sep 2017 01:01:02 +1000 (AEST)","from localhost ([::1]:59314 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dvPRs-0000Am-Fi\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 11:01:00 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:47013)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dvPQZ-0007xn-Lq\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:41 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dvPQY-00046p-Md\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:39 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37556)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dvPQW-00043B-CK; Fri, 22 Sep 2017 10:59:36 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from )\n\tid 1dvPQV-0007B3-A3; Fri, 22 Sep 2017 15:59:35 +0100"],"From":"Peter Maydell ","To":"qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Date":"Fri, 22 Sep 2017 15:59:55 +0100","Message-Id":"<1506092407-26985-9-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PATCH 08/20] target/arm: Don't warn about exception\n\treturn with PC low bit set for v8M","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"In the v8M architecture, return from an exception to a PC which\nhas bit 0 set is not UNPREDICTABLE; it is defined that bit 0\nis discarded [R_HRJH]. Restrict our complaint about this to v7M.\n\nSigned-off-by: Peter Maydell \n---\n target/arm/helper.c | 20 +++++++++++++-------\n 1 file changed, 13 insertions(+), 7 deletions(-)","diff":"diff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 979129e..59a07d2 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6421,16 +6421,22 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n env->regs[12] = ldl_phys(cs->as, frameptr + 0x10);\n env->regs[14] = ldl_phys(cs->as, frameptr + 0x14);\n env->regs[15] = ldl_phys(cs->as, frameptr + 0x18);\n- if (env->regs[15] & 1) {\n+\n+ /* Returning from an exception with a PC with bit 0 set is defined\n+ * behaviour on v8M (bit 0 is ignored), but for v7M it was specified\n+ * to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore\n+ * the lsbit, and there are several RTOSes out there which incorrectly\n+ * assume the r15 in the stack frame should be a Thumb-style \"lsbit\n+ * indicates ARM/Thumb\" value, so ignore the bit on v7M as well, but\n+ * complain about the badly behaved guest.\n+ */\n+ if ((env->regs[15] & 1) && !arm_feature(env, ARM_FEATURE_V8)) {\n qemu_log_mask(LOG_GUEST_ERROR,\n \"M profile return from interrupt with misaligned \"\n- \"PC is UNPREDICTABLE\\n\");\n- /* Actual hardware seems to ignore the lsbit, and there are several\n- * RTOSes out there which incorrectly assume the r15 in the stack\n- * frame should be a Thumb-style \"lsbit indicates ARM/Thumb\" value.\n- */\n- env->regs[15] &= ~1U;\n+ \"PC is UNPREDICTABLE on v7M\\n\");\n }\n+ env->regs[15] &= ~1U;\n+\n xpsr = ldl_phys(cs->as, frameptr + 0x1c);\n \n if (arm_feature(env, ARM_FEATURE_V8)) {\n","prefixes":["08/20"]}