{"id":817558,"url":"http://patchwork.ozlabs.org/api/patches/817558/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-2-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506092407-26985-2-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-22T14:59:48","name":"[01/20] nvic: Clear the vector arrays and prigroup on reset","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3c00e7f0773f2878e550a39b0976ed0463132c6d","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-2-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":4650,"url":"http://patchwork.ozlabs.org/api/series/4650/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4650","date":"2017-09-22T14:59:47","name":"ARM v8M: exception entry, exit and security","version":1,"mbox":"http://patchwork.ozlabs.org/series/4650/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/817558/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/817558/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzGrQ2FSSz9sNr\n\tfor ;\n\tSat, 23 Sep 2017 01:00:54 +1000 (AEST)","from localhost ([::1]:59310 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dvPRk-0008QF-AZ\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 11:00:52 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:46874)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dvPQW-0007tX-6h\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:37 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dvPQV-00042U-A3\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:36 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37534)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dvPQT-0003yz-5l; Fri, 22 Sep 2017 10:59:33 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from )\n\tid 1dvPQQ-00077x-HY; Fri, 22 Sep 2017 15:59:30 +0100"],"From":"Peter Maydell ","To":"qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Date":"Fri, 22 Sep 2017 15:59:48 +0100","Message-Id":"<1506092407-26985-2-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PATCH 01/20] nvic: Clear the vector arrays and\n\tprigroup on reset","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Reset for devices does not include an automatic clear of the\ndevice state (unlike CPU state, where most of the state\nstructure is cleared to zero). Add some missing initialization\nof NVIC state that meant that the device was left in the wrong\nstate if the guest did a warm reset.\n\n(In particular, since we were resetting the computed state like\ns->exception_prio but not all the state it was computed\nfrom like s->vectors[x].active, the NVIC wound up in an\ninconsistent state that could later trigger assertion failures.)\n\nSigned-off-by: Peter Maydell \n---\n hw/intc/armv7m_nvic.c | 5 +++++\n 1 file changed, 5 insertions(+)","diff":"diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex d90d8d0..bc7b66d 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -1782,6 +1782,11 @@ static void armv7m_nvic_reset(DeviceState *dev)\n int resetprio;\n NVICState *s = NVIC(dev);\n \n+ memset(s->vectors, 0, sizeof(s->vectors));\n+ memset(s->sec_vectors, 0, sizeof(s->sec_vectors));\n+ s->prigroup[M_REG_NS] = 0;\n+ s->prigroup[M_REG_S] = 0;\n+\n s->vectors[ARMV7M_EXCP_NMI].enabled = 1;\n /* MEM, BUS, and USAGE are enabled through\n * the System Handler Control register\n","prefixes":["01/20"]}