{"id":816980,"url":"http://patchwork.ozlabs.org/api/patches/816980/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506007346-10037-19-git-send-email-jjhiblot@ti.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506007346-10037-19-git-send-email-jjhiblot@ti.com>","list_archive_url":null,"date":"2017-09-21T15:22:21","name":"[U-Boot,18/23] ARM: OMAP5: set mmc clock frequency to 192MHz","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"96630551d471a15d9a14782887d64ca1b846926e","submitter":{"id":70508,"url":"http://patchwork.ozlabs.org/api/people/70508/?format=json","name":"Jean-Jacques Hiblot","email":"jjhiblot@ti.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506007346-10037-19-git-send-email-jjhiblot@ti.com/mbox/","series":[{"id":4414,"url":"http://patchwork.ozlabs.org/api/series/4414/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4414","date":"2017-09-21T15:22:03","name":"mmc: omap5: Add support for UHS and HS200 modes","version":1,"mbox":"http://patchwork.ozlabs.org/series/4414/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816980/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816980/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506007387;\n\tbh=Bf1kAeT4yEpPcezYK2+RzwF+dxoz6wSXrGVeBn2s9ro=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=vjqWAi0etdowOHB8nMMEntPG4XtJTR9NRPCQ08tZHiz5HKnQN4VhmLWXsA8Gz7muK\n\tQ52iN3T+y63ddq9xM8CQNXmugJCqLrL1OhIPlf2P3nCsVAa9NL/L+m/ZjKzNyEW5Bs\n\tyuIpAqdWjB9ukCupS4F+a7l6lcjXy7NNK/jd9Lps=","From":"Jean-Jacques Hiblot ","To":", , ,\n\t, ","Date":"Thu, 21 Sep 2017 17:22:21 +0200","Message-ID":"<1506007346-10037-19-git-send-email-jjhiblot@ti.com>","X-Mailer":"git-send-email 1.9.1","In-Reply-To":"<1506007346-10037-1-git-send-email-jjhiblot@ti.com>","References":"<1506007346-10037-1-git-send-email-jjhiblot@ti.com>","MIME-Version":"1.0","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Cc":"u-boot@lists.denx.de","Subject":"[U-Boot] [PATCH 18/23] ARM: OMAP5: set mmc clock frequency to 192MHz","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Kishon Vijay Abraham I \n\nNow that omap_hsmmc has support for hs200 mode, change the clock\nfrequency to 192MHz. Also change the REFERENCE CLOCK frequency to\n192MHz based on which the internal mmc clock divider is calculated.\n\nSigned-off-by: Kishon Vijay Abraham I \nSigned-off-by: Jean-Jacques Hiblot \n---\n arch/arm/include/asm/arch-omap5/clock.h | 2 +-\n arch/arm/include/asm/omap_mmc.h | 4 ++++\n arch/arm/mach-omap2/omap5/hw_data.c | 10 +++++-----\n 3 files changed, 10 insertions(+), 6 deletions(-)","diff":"diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h\nindex ee2e78b..3d718c0 100644\n--- a/arch/arm/include/asm/arch-omap5/clock.h\n+++ b/arch/arm/include/asm/arch-omap5/clock.h\n@@ -135,7 +135,7 @@\n \n /* CM_L3INIT_HSMMCn_CLKCTRL */\n #define HSMMC_CLKCTRL_CLKSEL_MASK\t\t(1 << 24)\n-#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK\t\t(1 << 25)\n+#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK\t\t(3 << 25)\n \n /* CM_L3INIT_SATA_CLKCTRL */\n #define SATA_CLKCTRL_OPTFCLKEN_MASK\t\t(1 << 8)\ndiff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h\nindex 6871f54..d604b79 100644\n--- a/arch/arm/include/asm/omap_mmc.h\n+++ b/arch/arm/include/asm/omap_mmc.h\n@@ -199,7 +199,11 @@ struct omap_hsmmc_plat {\n #define MMC_CMD0\t(INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)\n \n /* Clock Configurations and Macros */\n+#ifdef CONFIG_OMAP54XX\n+#define MMC_CLOCK_REFERENCE\t192 /* MHz */\n+#else\n #define MMC_CLOCK_REFERENCE\t96 /* MHz */\n+#endif\n \n /* DLL */\n #define DLL_SWT\t\t\t(1 << 20)\ndiff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c\nindex 3bdb114..30e3b68 100644\n--- a/arch/arm/mach-omap2/omap5/hw_data.c\n+++ b/arch/arm/mach-omap2/omap5/hw_data.c\n@@ -438,17 +438,17 @@ void enable_basic_clocks(void)\n \tsetbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,\n \t\t\tGPIO4_CLKCTRL_OPTFCLKEN_MASK);\n \n-\t/* Enable 96 MHz clock for MMC1 & MMC2 */\n+\t/* Enable 192 MHz clock for MMC1 & MMC2 */\n \tsetbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,\n \t\t\tHSMMC_CLKCTRL_CLKSEL_MASK);\n \tsetbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,\n \t\t\tHSMMC_CLKCTRL_CLKSEL_MASK);\n \n \t/* Set the correct clock dividers for mmc */\n-\tsetbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,\n-\t\t\tHSMMC_CLKCTRL_CLKSEL_DIV_MASK);\n-\tsetbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,\n-\t\t\tHSMMC_CLKCTRL_CLKSEL_DIV_MASK);\n+\tclrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,\n+\t\t HSMMC_CLKCTRL_CLKSEL_DIV_MASK);\n+\tclrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,\n+\t\t HSMMC_CLKCTRL_CLKSEL_DIV_MASK);\n \n \t/* Select 32KHz clock as the source of GPTIMER1 */\n \tsetbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,\n","prefixes":["U-Boot","18/23"]}