{"id":816957,"url":"http://patchwork.ozlabs.org/api/patches/816957/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506007346-10037-9-git-send-email-jjhiblot@ti.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506007346-10037-9-git-send-email-jjhiblot@ti.com>","list_archive_url":null,"date":"2017-09-21T15:22:11","name":"[U-Boot,08/23] mmc: omap_hsmmc: Reduce the max timeout for reset controller fsm","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"c92573493fb2e68e189ae75498d01e01b0c19a63","submitter":{"id":70508,"url":"http://patchwork.ozlabs.org/api/people/70508/?format=json","name":"Jean-Jacques Hiblot","email":"jjhiblot@ti.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506007346-10037-9-git-send-email-jjhiblot@ti.com/mbox/","series":[{"id":4414,"url":"http://patchwork.ozlabs.org/api/series/4414/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4414","date":"2017-09-21T15:22:03","name":"mmc: omap5: Add support for UHS and HS200 modes","version":1,"mbox":"http://patchwork.ozlabs.org/series/4414/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816957/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816957/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506007370;\n\tbh=WNI9S5DbZG8G0OiOMBfCp04jGYcI4tk4jXwInG5v5JY=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=NKVnteWQnRQrjnLLWjR6LVx5MLX9+aicMBTTYvSYm1yrko19zmJ/4fhVqw1wwJnsv\n\tQoyY9bveM5Chf/azWI3KW8fBiU/BdDd5VG5XwN3bsfLfriasqE5VQYaRBz7Vjfdlse\n\t9aYVz+pwQ9bexWx35SIEmOXXAoiyobl7auQCdsZU=","From":"Jean-Jacques Hiblot ","To":", , ,\n\t, ","Date":"Thu, 21 Sep 2017 17:22:11 +0200","Message-ID":"<1506007346-10037-9-git-send-email-jjhiblot@ti.com>","X-Mailer":"git-send-email 1.9.1","In-Reply-To":"<1506007346-10037-1-git-send-email-jjhiblot@ti.com>","References":"<1506007346-10037-1-git-send-email-jjhiblot@ti.com>","MIME-Version":"1.0","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Cc":"u-boot@lists.denx.de","Subject":"[U-Boot] [PATCH 08/23] mmc: omap_hsmmc: Reduce the max timeout for\n\treset controller fsm","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From OMAP3 SoCs (OMAP3, OMAP4, OMAP5, AM572x, AM571x), the DAT/CMD lines\nreset procedure section in TRM suggests to first poll the SRD/SRC bit\nuntil it is set to 0x1. But looks like that bit is never set to 1 and there\nis an observable delay of 1sec everytime the driver tries to reset DAT/CMD.\n(The same is observed in linux kernel).\n\nReduce the time the driver waits for the controller to set the SRC/SRD bits\nto 1 so that there is no observable delay.\n\nSigned-off-by: Kishon Vijay Abraham I \nSigned-off-by: Jean-Jacques Hiblot \n---\n drivers/mmc/omap_hsmmc.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c\nindex 8e42410..116aa31 100644\n--- a/drivers/mmc/omap_hsmmc.c\n+++ b/drivers/mmc/omap_hsmmc.c\n@@ -108,6 +108,7 @@ struct omap_hsmmc_adma_desc {\n \n /* If we fail after 1 second wait, something is really bad */\n #define MAX_RETRY_MS\t1000\n+#define MMC_TIMEOUT_MS\t20\n \n /* DMA transfers can take a long time if a lot a data is transfered.\n * The timeout must take in account the amount of data. Let's assume\n@@ -596,7 +597,7 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)\n \tif (!(readl(&mmc_base->sysctl) & bit)) {\n \t\tstart = get_timer(0);\n \t\twhile (!(readl(&mmc_base->sysctl) & bit)) {\n-\t\t\tif (get_timer(0) - start > MAX_RETRY_MS)\n+\t\t\tif (get_timer(0) - start > MMC_TIMEOUT_MS)\n \t\t\t\treturn;\n \t\t}\n \t}\n","prefixes":["U-Boot","08/23"]}