{"id":816902,"url":"http://patchwork.ozlabs.org/api/patches/816902/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506004213-22620-12-git-send-email-jjhiblot@ti.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506004213-22620-12-git-send-email-jjhiblot@ti.com>","list_archive_url":null,"date":"2017-09-21T14:29:58","name":"[U-Boot,v2,11/26] mmc: refactor MMC startup to make it easier to support new modes","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"00dc220f1f2a86e74913e3f208225fafd24eaae4","submitter":{"id":70508,"url":"http://patchwork.ozlabs.org/api/people/70508/?format=json","name":"Jean-Jacques Hiblot","email":"jjhiblot@ti.com"},"delegate":{"id":12423,"url":"http://patchwork.ozlabs.org/api/users/12423/?format=json","username":"Jaehoon","first_name":"Jaehoon","last_name":"Chung","email":"jh80.chung@samsung.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506004213-22620-12-git-send-email-jjhiblot@ti.com/mbox/","series":[{"id":4400,"url":"http://patchwork.ozlabs.org/api/series/4400/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4400","date":"2017-09-21T14:29:47","name":"mmc: Add support for HS200 and UHS modes","version":2,"mbox":"http://patchwork.ozlabs.org/series/4400/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816902/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816902/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"RVjQuaA5\";\n\tdkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyfQT4dkdz9t3C\n\tfor ;\n\tFri, 22 Sep 2017 00:39:45 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 549E6C22012; Thu, 21 Sep 2017 14:36:50 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 25BFDC21DD0;\n\tThu, 21 Sep 2017 14:33:23 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid CF8ACC22022; Thu, 21 Sep 2017 14:31:55 +0000 (UTC)","from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16])\n\tby lists.denx.de (Postfix) with ESMTPS id B2C6BC21FE8\n\tfor ; Thu, 21 Sep 2017 14:31:49 +0000 (UTC)","from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LEUlfF032472; \n\tThu, 21 Sep 2017 09:30:47 -0500","from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEUgeP019765; \n\tThu, 21 Sep 2017 09:30:42 -0500","from DFLE101.ent.ti.com (10.64.6.22) by DFLE103.ent.ti.com\n\t(10.64.6.24) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tThu, 21 Sep 2017 09:30:42 -0500","from dlep33.itg.ti.com (157.170.170.75) by DFLE101.ent.ti.com\n\t(10.64.6.22) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Thu, 21 Sep 2017 09:30:42 -0500","from localhost (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEUefo011490;\n\tThu, 21 Sep 2017 09:30:41 -0500"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506004247;\n\tbh=yAlaK4Oy5GdB0ngQ9qYpcFEGv4Yqw/moJySCTnY727s=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=RVjQuaA53cUB3vGLal4G/Ag2UKqdlbXzKDZXSahpO86pn/47L5KM2XfDW83oTHmD2\n\taO8bCuTlDKXYjSxA3rDtJFUx/hL8t6cfhMNn30zLt7zrf42R9StqHmnVKhfj9t+1CN\n\tEcrCYtZnGbw6rDZlacJwePPjTZwDb3VjwMNDooiw=","From":"Jean-Jacques Hiblot ","To":", , ,\n\t","Date":"Thu, 21 Sep 2017 16:29:58 +0200","Message-ID":"<1506004213-22620-12-git-send-email-jjhiblot@ti.com>","X-Mailer":"git-send-email 1.9.1","In-Reply-To":"<1506004213-22620-1-git-send-email-jjhiblot@ti.com>","References":"<1506004213-22620-1-git-send-email-jjhiblot@ti.com>","MIME-Version":"1.0","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Cc":"u-boot@lists.denx.de","Subject":"[U-Boot] [PATCH v2 11/26] mmc: refactor MMC startup to make it\n\teasier to support new modes","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"The MMC startup process currently handles 4 modes. To make it easier to\nadd support for more modes, let's make the process more generic and use a\nlist of the modes to try.\nThe major functional change is that when a mode fails we try the next one.\nNot all modes are tried, only those supported by the card and the host.\n\nSigned-off-by: Jean-Jacques Hiblot \nReviewed-by: Simon Glass \n---\n drivers/mmc/mmc.c | 241 +++++++++++++++++++++++++++++++++---------------------\n include/mmc.h | 11 +++\n 2 files changed, 158 insertions(+), 94 deletions(-)","diff":"diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c\nindex b8e726a..7361447 100644\n--- a/drivers/mmc/mmc.c\n+++ b/drivers/mmc/mmc.c\n@@ -202,6 +202,7 @@ static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)\n {\n \tmmc->selected_mode = mode;\n \tmmc->tran_speed = mmc_mode2freq(mmc, mode);\n+\tmmc->ddr_mode = mmc_is_mode_ddr(mode);\n \tdebug(\"selecting mode %s (freq : %d MHz)\\n\", mmc_mode_name(mode),\n \t mmc->tran_speed / 1000000);\n \treturn 0;\n@@ -605,11 +606,47 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)\n \n }\n \n-static int mmc_change_freq(struct mmc *mmc)\n+static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)\n {\n-\tALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);\n-\tchar cardtype;\n \tint err;\n+\tint speed_bits;\n+\n+\tALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);\n+\n+\tswitch (mode) {\n+\tcase MMC_HS:\n+\tcase MMC_HS_52:\n+\tcase MMC_DDR_52:\n+\t\tspeed_bits = EXT_CSD_TIMING_HS;\n+\tcase MMC_LEGACY:\n+\t\tspeed_bits = EXT_CSD_TIMING_LEGACY;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\terr = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,\n+\t\t\t speed_bits);\n+\tif (err)\n+\t\treturn err;\n+\n+\tif ((mode == MMC_HS) || (mode == MMC_HS_52)) {\n+\t\t/* Now check to see that it worked */\n+\t\terr = mmc_send_ext_csd(mmc, test_csd);\n+\t\tif (err)\n+\t\t\treturn err;\n+\n+\t\t/* No high-speed support */\n+\t\tif (!test_csd[EXT_CSD_HS_TIMING])\n+\t\t\treturn -ENOTSUPP;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mmc_get_capabilities(struct mmc *mmc)\n+{\n+\tu8 *ext_csd = mmc->ext_csd;\n+\tchar cardtype;\n \n \tmmc->card_caps = MMC_MODE_1BIT;\n \n@@ -620,38 +657,23 @@ static int mmc_change_freq(struct mmc *mmc)\n \tif (mmc->version < MMC_VERSION_4)\n \t\treturn 0;\n \n-\tmmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;\n-\n-\terr = mmc_send_ext_csd(mmc, ext_csd);\n+\tif (!ext_csd) {\n+\t\terror(\"No ext_csd found!\\n\"); /* this should enver happen */\n+\t\treturn -ENOTSUPP;\n+\t}\n \n-\tif (err)\n-\t\treturn err;\n+\tmmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;\n \n \tcardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;\n \n-\terr = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);\n-\n-\tif (err)\n-\t\treturn err;\n-\n-\t/* Now check to see that it worked */\n-\terr = mmc_send_ext_csd(mmc, ext_csd);\n-\n-\tif (err)\n-\t\treturn err;\n-\n-\t/* No high-speed support */\n-\tif (!ext_csd[EXT_CSD_HS_TIMING])\n-\t\treturn 0;\n-\n \t/* High Speed is set, there are two types: 52MHz and 26MHz */\n \tif (cardtype & EXT_CSD_CARD_TYPE_52) {\n-\t\tif (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)\n+\t\tif (cardtype & EXT_CSD_CARD_TYPE_DDR_52)\n \t\t\tmmc->card_caps |= MMC_MODE_DDR_52MHz;\n-\t\tmmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;\n-\t} else {\n-\t\tmmc->card_caps |= MMC_MODE_HS;\n+\t\tmmc->card_caps |= MMC_MODE_HS_52MHz;\n \t}\n+\tif (cardtype & EXT_CSD_CARD_TYPE_26)\n+\t\tmmc->card_caps |= MMC_MODE_HS;\n \n \treturn 0;\n }\n@@ -1334,33 +1356,60 @@ static int mmc_read_and_compare_ext_csd(struct mmc *mmc)\n \treturn -EBADMSG;\n }\n \n-static int mmc_select_bus_freq_width(struct mmc *mmc)\n+static const struct mode_width_tuning mmc_modes_by_pref[] = {\n+\t{\n+\t\t.mode = MMC_HS_200,\n+\t\t.widths = MMC_MODE_8BIT | MMC_MODE_4BIT,\n+\t},\n+\t{\n+\t\t.mode = MMC_DDR_52,\n+\t\t.widths = MMC_MODE_8BIT | MMC_MODE_4BIT,\n+\t},\n+\t{\n+\t\t.mode = MMC_HS_52,\n+\t\t.widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,\n+\t},\n+\t{\n+\t\t.mode = MMC_HS,\n+\t\t.widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,\n+\t},\n+\t{\n+\t\t.mode = MMC_LEGACY,\n+\t\t.widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,\n+\t}\n+};\n+\n+#define for_each_mmc_mode_by_pref(caps, mwt) \\\n+\tfor (mwt = mmc_modes_by_pref;\\\n+\t mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\\\n+\t mwt++) \\\n+\t\tif (caps & MMC_CAP(mwt->mode))\n+\n+static const struct ext_csd_bus_width {\n+\tuint cap;\n+\tbool is_ddr;\n+\tuint ext_csd_bits;\n+} ext_csd_bus_width[] = {\n+\t{MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},\n+\t{MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},\n+\t{MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},\n+\t{MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},\n+\t{MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},\n+};\n+\n+#define for_each_supported_width(caps, ddr, ecbv) \\\n+\tfor (ecbv = ext_csd_bus_width;\\\n+\t ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\\\n+\t ecbv++) \\\n+\t\tif ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))\n+\n+static int mmc_select_mode_and_width(struct mmc *mmc)\n {\n-\t/* An array of possible bus widths in order of preference */\n-\tstatic const unsigned int ext_csd_bits[] = {\n-\t\tEXT_CSD_DDR_BUS_WIDTH_8,\n-\t\tEXT_CSD_DDR_BUS_WIDTH_4,\n-\t\tEXT_CSD_BUS_WIDTH_8,\n-\t\tEXT_CSD_BUS_WIDTH_4,\n-\t\tEXT_CSD_BUS_WIDTH_1,\n-\t};\n-\t/* An array to map CSD bus widths to host cap bits */\n-\tstatic const unsigned int ext_to_hostcaps[] = {\n-\t\t[EXT_CSD_DDR_BUS_WIDTH_4] =\n-\t\t\tMMC_MODE_DDR_52MHz | MMC_MODE_4BIT,\n-\t\t[EXT_CSD_DDR_BUS_WIDTH_8] =\n-\t\t\tMMC_MODE_DDR_52MHz | MMC_MODE_8BIT,\n-\t\t[EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,\n-\t\t[EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,\n-\t};\n-\t/* An array to map chosen bus width to an integer */\n-\tstatic const unsigned int widths[] = {\n-\t\t8, 4, 8, 4, 1,\n-\t};\n \tint err;\n-\tint idx;\n+\tconst struct mode_width_tuning *mwt;\n+\tconst struct ext_csd_bus_width *ecbw;\n \n-\terr = mmc_change_freq(mmc);\n+\terr = mmc_get_capabilities(mmc);\n \tif (err)\n \t\treturn err;\n \n@@ -1376,54 +1425,58 @@ static int mmc_select_bus_freq_width(struct mmc *mmc)\n \t\treturn -ENOTSUPP;\n \t}\n \n-\tfor (idx = 0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {\n-\t\tunsigned int extw = ext_csd_bits[idx];\n-\t\tunsigned int caps = ext_to_hostcaps[extw];\n-\t\t/*\n-\t\t * If the bus width is still not changed,\n-\t\t * don't try to set the default again.\n-\t\t * Otherwise, recover from switch attempts\n-\t\t * by switching to 1-bit bus width.\n-\t\t */\n-\t\tif (extw == EXT_CSD_BUS_WIDTH_1 &&\n-\t\t mmc->bus_width == 1) {\n-\t\t\terr = 0;\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\t/*\n-\t\t * Check to make sure the card and controller support\n-\t\t * these capabilities\n-\t\t */\n-\t\tif ((mmc->card_caps & caps) != caps)\n-\t\t\tcontinue;\n-\n-\t\terr = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,\n-\t\t\t\t EXT_CSD_BUS_WIDTH, extw);\n+\tfor_each_mmc_mode_by_pref(mmc->card_caps, mwt) {\n+\t\tfor_each_supported_width(mmc->card_caps & mwt->widths,\n+\t\t\t\t\t mmc_is_mode_ddr(mwt->mode), ecbw) {\n+\t\t\tdebug(\"trying mode %s width %d (at %d MHz)\\n\",\n+\t\t\t mmc_mode_name(mwt->mode),\n+\t\t\t bus_width(ecbw->cap),\n+\t\t\t mmc_mode2freq(mmc, mwt->mode) / 1000000);\n+\t\t\t/* configure the bus width (card + host) */\n+\t\t\terr = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,\n+\t\t\t\t EXT_CSD_BUS_WIDTH,\n+\t\t\t\t ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);\n+\t\t\tif (err)\n+\t\t\t\tgoto error;\n+\t\t\tmmc_set_bus_width(mmc, bus_width(ecbw->cap));\n \n-\t\tif (err)\n-\t\t\tcontinue;\n+\t\t\t/* configure the bus speed (card) */\n+\t\t\terr = mmc_set_card_speed(mmc, mwt->mode);\n+\t\t\tif (err)\n+\t\t\t\tgoto error;\n+\n+\t\t\t/*\n+\t\t\t * configure the bus width AND the ddr mode (card)\n+\t\t\t * The host side will be taken care of in the next step\n+\t\t\t */\n+\t\t\tif (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {\n+\t\t\t\terr = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,\n+\t\t\t\t\t\t EXT_CSD_BUS_WIDTH,\n+\t\t\t\t\t\t ecbw->ext_csd_bits);\n+\t\t\t\tif (err)\n+\t\t\t\t\tgoto error;\n+\t\t\t}\n \n-\t\tmmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;\n-\t\tmmc_set_bus_width(mmc, widths[idx]);\n+\t\t\t/* configure the bus mode (host) */\n+\t\t\tmmc_select_mode(mmc, mwt->mode);\n+\t\t\tmmc_set_clock(mmc, mmc->tran_speed);\n \n-\t\terr = mmc_read_and_compare_ext_csd(mmc);\n-\t\tif (!err)\n-\t\t\tbreak;\n+\t\t\t/* do a transfer to check the configuration */\n+\t\t\terr = mmc_read_and_compare_ext_csd(mmc);\n+\t\t\tif (!err)\n+\t\t\t\treturn 0;\n+error:\n+\t\t\t/* if an error occured, revert to a safer bus mode */\n+\t\t\tmmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,\n+\t\t\t\t EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);\n+\t\t\tmmc_select_mode(mmc, MMC_LEGACY);\n+\t\t\tmmc_set_bus_width(mmc, 1);\n+\t\t}\n \t}\n \n-\tif (err)\n-\t\treturn err;\n-\n-\tif (mmc->card_caps & MMC_MODE_HS_52MHz) {\n-\t\tif (mmc->ddr_mode)\n-\t\t\tmmc_select_mode(mmc, MMC_DDR_52);\n-\t\telse\n-\t\t\tmmc_select_mode(mmc, MMC_HS_52);\n-\t} else if (mmc->card_caps & MMC_MODE_HS)\n-\t\tmmc_select_mode(mmc, MMC_HS);\n+\terror(\"unable to select a mode\\n\");\n \n-\treturn err;\n+\treturn -ENOTSUPP;\n }\n \n static int mmc_startup_v4(struct mmc *mmc)\n@@ -1762,7 +1815,7 @@ static int mmc_startup(struct mmc *mmc)\n \tif (IS_SD(mmc))\n \t\terr = sd_select_mode_and_width(mmc);\n \telse\n-\t\terr = mmc_select_bus_freq_width(mmc);\n+\t\terr = mmc_select_mode_and_width(mmc);\n \n \tif (err)\n \t\treturn err;\ndiff --git a/include/mmc.h b/include/mmc.h\nindex 9fe6a87..988bf17 100644\n--- a/include/mmc.h\n+++ b/include/mmc.h\n@@ -215,7 +215,10 @@\n #define EXT_CSD_BUS_WIDTH_8\t2\t/* Card is in 8 bit mode */\n #define EXT_CSD_DDR_BUS_WIDTH_4\t5\t/* Card is in 4 bit DDR mode */\n #define EXT_CSD_DDR_BUS_WIDTH_8\t6\t/* Card is in 8 bit DDR mode */\n+#define EXT_CSD_DDR_FLAG\tBIT(2)\t/* Flag for DDR mode */\n \n+#define EXT_CSD_TIMING_LEGACY\t0\t/* no high speed */\n+#define EXT_CSD_TIMING_HS\t1\t/* HS */\n #define EXT_CSD_BOOT_ACK_ENABLE\t\t\t(1 << 6)\n #define EXT_CSD_BOOT_PARTITION_ENABLE\t\t(1 << 3)\n #define EXT_CSD_PARTITION_ACCESS_ENABLE\t\t(1 << 0)\n@@ -429,6 +432,14 @@ enum bus_mode {\n const char *mmc_mode_name(enum bus_mode mode);\n void mmc_dump_capabilities(const char *text, uint caps);\n \n+static inline bool mmc_is_mode_ddr(enum bus_mode mode)\n+{\n+\tif ((mode == MMC_DDR_52) || (mode == UHS_DDR50))\n+\t\treturn true;\n+\telse\n+\t\treturn false;\n+}\n+\n /*\n * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device\n * with mmc_get_mmc_dev().\n","prefixes":["U-Boot","v2","11/26"]}