{"id":816898,"url":"http://patchwork.ozlabs.org/api/patches/816898/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506004213-22620-7-git-send-email-jjhiblot@ti.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506004213-22620-7-git-send-email-jjhiblot@ti.com>","list_archive_url":null,"date":"2017-09-21T14:29:53","name":"[U-Boot,v2,06/26] mmc: introduce mmc modes","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"6df3ebff4379f38fed3e99d6a7838bebf0ea6cfc","submitter":{"id":70508,"url":"http://patchwork.ozlabs.org/api/people/70508/?format=json","name":"Jean-Jacques Hiblot","email":"jjhiblot@ti.com"},"delegate":{"id":12423,"url":"http://patchwork.ozlabs.org/api/users/12423/?format=json","username":"Jaehoon","first_name":"Jaehoon","last_name":"Chung","email":"jh80.chung@samsung.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506004213-22620-7-git-send-email-jjhiblot@ti.com/mbox/","series":[{"id":4400,"url":"http://patchwork.ozlabs.org/api/series/4400/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4400","date":"2017-09-21T14:29:47","name":"mmc: Add support for HS200 and UHS modes","version":2,"mbox":"http://patchwork.ozlabs.org/series/4400/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816898/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816898/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"AFxMznpz\";\n\tdkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyfP05NKpz9sNc\n\tfor ;\n\tFri, 22 Sep 2017 00:38:28 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 8738BC21F49; Thu, 21 Sep 2017 14:32:26 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 1DC70C22026;\n\tThu, 21 Sep 2017 14:30:51 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 5F353C21E3B; Thu, 21 Sep 2017 14:30:39 +0000 (UTC)","from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77])\n\tby lists.denx.de (Postfix) with ESMTPS id 83709C21F7D\n\tfor ; Thu, 21 Sep 2017 14:30:35 +0000 (UTC)","from dflxv15.itg.ti.com ([128.247.5.124])\n\tby lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LEUVfa029437; \n\tThu, 21 Sep 2017 09:30:31 -0500","from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEUVol028350;\n\tThu, 21 Sep 2017 09:30:31 -0500","from DFLE106.ent.ti.com (10.64.6.27) by DFLE100.ent.ti.com\n\t(10.64.6.21) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tThu, 21 Sep 2017 09:30:31 -0500","from dflp32.itg.ti.com (10.64.6.15) by DFLE106.ent.ti.com\n\t(10.64.6.27) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Thu, 21 Sep 2017 09:30:31 -0500","from localhost (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEUUqi016291;\n\tThu, 21 Sep 2017 09:30:30 -0500"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506004231;\n\tbh=hq+dRHOewD15jorSu6VWDU+rlZlFtYR6HaNujepXaYM=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=AFxMznpzPIGos1xTMVLj8YgxNx/dZx/bWV4i2/7CYjNMS8tZbGj5JJmH3wPnpaQlX\n\tnvwWctoQ1lAm4l7RVLqoMOHvtpVDnaOHs8v9vKjEY+tY8AJp03Q7SAizybgu+GmFxK\n\tGCEz/Hgmn5NH3quRaQbr7A9tIaiWcZYZ01YXmSE4=","From":"Jean-Jacques Hiblot ","To":", , ,\n\t","Date":"Thu, 21 Sep 2017 16:29:53 +0200","Message-ID":"<1506004213-22620-7-git-send-email-jjhiblot@ti.com>","X-Mailer":"git-send-email 1.9.1","In-Reply-To":"<1506004213-22620-1-git-send-email-jjhiblot@ti.com>","References":"<1506004213-22620-1-git-send-email-jjhiblot@ti.com>","MIME-Version":"1.0","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Cc":"u-boot@lists.denx.de","Subject":"[U-Boot] [PATCH v2 06/26] mmc: introduce mmc modes","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"no functionnal changes.\nIn order to add the support for the high speed SD and MMC modes, it is\nuseful to track this information.\n\nSigned-off-by: Jean-Jacques Hiblot \nReviewed-by: Simon Glass \n---\n drivers/mmc/Kconfig | 14 ++++++++++++++\n drivers/mmc/mmc.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++-------\n include/mmc.h | 35 +++++++++++++++++++++++++++------\n 3 files changed, 92 insertions(+), 13 deletions(-)","diff":"diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig\nindex 6de927b..3d577e0 100644\n--- a/drivers/mmc/Kconfig\n+++ b/drivers/mmc/Kconfig\n@@ -33,6 +33,20 @@ config SPL_DM_MMC\n \n if MMC\n \n+config MMC_VERBOSE\n+\tbool \"Output more information about the MMC\"\n+\tdefault y\n+\thelp\n+\t Enable the output of more information about the card such as the\n+\t operating mode.\n+\n+config SPL_MMC_VERBOSE\n+\tbool \"Output more information about the MMC in SPL\"\n+\tdefault n\n+\thelp\n+\t Enable the output of more information about the card such as the\n+\t operating mode.\n+\n config SPL_MMC_TINY\n \tbool \"Tiny MMC framework in SPL\"\n \thelp\ndiff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c\nindex d360a1a..94b3a02 100644\n--- a/drivers/mmc/mmc.c\n+++ b/drivers/mmc/mmc.c\n@@ -149,6 +149,39 @@ void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)\n }\n #endif\n \n+#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)\n+const char *mmc_mode_name(enum bus_mode mode)\n+{\n+\tstatic const char *const names[] = {\n+\t [MMC_LEGACY]\t= \"MMC legacy\",\n+\t [SD_LEGACY]\t= \"SD Legacy\",\n+\t [MMC_HS]\t\t= \"MMC High Speed (26MHz)\",\n+\t [SD_HS]\t\t= \"SD High Speed (50MHz)\",\n+\t [UHS_SDR12]\t= \"UHS SDR12 (25MHz)\",\n+\t [UHS_SDR25]\t= \"UHS SDR25 (50MHz)\",\n+\t [UHS_SDR50]\t= \"UHS SDR50 (100MHz)\",\n+\t [UHS_SDR104]\t= \"UHS SDR104 (208MHz)\",\n+\t [UHS_DDR50]\t= \"UHS DDR50 (50MHz)\",\n+\t [MMC_HS_52]\t= \"MMC High Speed (52MHz)\",\n+\t [MMC_DDR_52]\t= \"MMC DDR52 (52MHz)\",\n+\t [MMC_HS_200]\t= \"HS200 (200MHz)\",\n+\t};\n+\n+\tif (mode >= MMC_MODES_END)\n+\t\treturn \"Unknown mode\";\n+\telse\n+\t\treturn names[mode];\n+}\n+#endif\n+\n+static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)\n+{\n+\tmmc->selected_mode = mode;\n+\tdebug(\"selecting mode %s (freq : %d MHz)\\n\", mmc_mode_name(mode),\n+\t mmc->tran_speed / 1000000);\n+\treturn 0;\n+}\n+\n #if !CONFIG_IS_ENABLED(DM_MMC)\n int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)\n {\n@@ -1138,10 +1171,13 @@ static int sd_select_bus_freq_width(struct mmc *mmc)\n \tif (err)\n \t\treturn err;\n \n-\tif (mmc->card_caps & MMC_MODE_HS)\n+\tif (mmc->card_caps & MMC_MODE_HS) {\n+\t\tmmc_select_mode(mmc, SD_HS);\n \t\tmmc->tran_speed = 50000000;\n-\telse\n+\t} else {\n+\t\tmmc_select_mode(mmc, SD_LEGACY);\n \t\tmmc->tran_speed = 25000000;\n+\t}\n \n \treturn 0;\n }\n@@ -1258,11 +1294,15 @@ static int mmc_select_bus_freq_width(struct mmc *mmc)\n \tif (err)\n \t\treturn err;\n \n-\tif (mmc->card_caps & MMC_MODE_HS) {\n-\t\tif (mmc->card_caps & MMC_MODE_HS_52MHz)\n-\t\t\tmmc->tran_speed = 52000000;\n+\tif (mmc->card_caps & MMC_MODE_HS_52MHz) {\n+\t\tif (mmc->ddr_mode)\n+\t\t\tmmc_select_mode(mmc, MMC_DDR_52);\n \t\telse\n-\t\t\tmmc->tran_speed = 26000000;\n+\t\t\tmmc_select_mode(mmc, MMC_HS_52);\n+\t\tmmc->tran_speed = 52000000;\n+\t} else if (mmc->card_caps & MMC_MODE_HS) {\n+\t\tmmc_select_mode(mmc, MMC_HS);\n+\t\tmmc->tran_speed = 26000000;\n \t}\n \n \treturn err;\n@@ -1534,7 +1574,9 @@ static int mmc_startup(struct mmc *mmc)\n \tfreq = fbase[(cmd.response[0] & 0x7)];\n \tmult = multipliers[((cmd.response[0] >> 3) & 0xf)];\n \n-\tmmc->tran_speed = freq * mult;\n+\tmmc->legacy_speed = freq * mult;\n+\tmmc->tran_speed = mmc->legacy_speed;\n+\tmmc_select_mode(mmc, MMC_LEGACY);\n \n \tmmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);\n \tmmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);\ndiff --git a/include/mmc.h b/include/mmc.h\nindex 7d2b363..76bd57a 100644\n--- a/include/mmc.h\n+++ b/include/mmc.h\n@@ -52,12 +52,15 @@\n #define MMC_VERSION_5_0\t\tMAKE_MMC_VERSION(5, 0, 0)\n #define MMC_VERSION_5_1\t\tMAKE_MMC_VERSION(5, 1, 0)\n \n-#define MMC_MODE_HS\t\t(1 << 0)\n-#define MMC_MODE_HS_52MHz\t(1 << 1)\n-#define MMC_MODE_4BIT\t\t(1 << 2)\n-#define MMC_MODE_8BIT\t\t(1 << 3)\n-#define MMC_MODE_SPI\t\t(1 << 4)\n-#define MMC_MODE_DDR_52MHz\t(1 << 5)\n+#define MMC_CAP(mode)\t\t(1 << mode)\n+#define MMC_MODE_HS\t\t(MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))\n+#define MMC_MODE_HS_52MHz\tMMC_CAP(MMC_HS_52)\n+#define MMC_MODE_DDR_52MHz\tMMC_CAP(MMC_DDR_52)\n+\n+#define MMC_MODE_8BIT\t\tBIT(30)\n+#define MMC_MODE_4BIT\t\tBIT(29)\n+#define MMC_MODE_SPI\t\tBIT(27)\n+\n \n #define SD_DATA_4BIT\t0x00040000\n \n@@ -406,6 +409,24 @@ struct sd_ssr {\n \tunsigned int erase_offset;\t/* In milliseconds */\n };\n \n+enum bus_mode {\n+\tMMC_LEGACY,\n+\tSD_LEGACY,\n+\tMMC_HS,\n+\tSD_HS,\n+\tUHS_SDR12,\n+\tUHS_SDR25,\n+\tUHS_SDR50,\n+\tUHS_SDR104,\n+\tUHS_DDR50,\n+\tMMC_HS_52,\n+\tMMC_DDR_52,\n+\tMMC_HS_200,\n+\tMMC_MODES_END\n+};\n+\n+const char *mmc_mode_name(enum bus_mode mode);\n+\n /*\n * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device\n * with mmc_get_mmc_dev().\n@@ -436,6 +457,7 @@ struct mmc {\n \tu8 wr_rel_set;\n \tu8 part_config;\n \tuint tran_speed;\n+\tuint legacy_speed; /* speed for the legacy mode provided by the card */\n \tuint read_bl_len;\n \tuint write_bl_len;\n \tuint erase_grp_size;\t/* in 512-byte sectors */\n@@ -463,6 +485,7 @@ struct mmc {\n #endif\n #endif\n \tu8 *ext_csd;\n+\tenum bus_mode selected_mode;\n };\n \n struct mmc_hwpart_conf {\n","prefixes":["U-Boot","v2","06/26"]}