{"id":816894,"url":"http://patchwork.ozlabs.org/api/patches/816894/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506004213-22620-3-git-send-email-jjhiblot@ti.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1506004213-22620-3-git-send-email-jjhiblot@ti.com>","list_archive_url":null,"date":"2017-09-21T14:29:49","name":"[U-Boot,v2,02/26] mmc: split mmc_startup()","commit_ref":"8ac8a2630459bacb2d9b6516d49bedad61ca63f8","pull_url":null,"state":"accepted","archived":false,"hash":"915acc96c379884e224d174d553dd436d7331da2","submitter":{"id":70508,"url":"http://patchwork.ozlabs.org/api/people/70508/?format=json","name":"Jean-Jacques Hiblot","email":"jjhiblot@ti.com"},"delegate":{"id":12423,"url":"http://patchwork.ozlabs.org/api/users/12423/?format=json","username":"Jaehoon","first_name":"Jaehoon","last_name":"Chung","email":"jh80.chung@samsung.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506004213-22620-3-git-send-email-jjhiblot@ti.com/mbox/","series":[{"id":4400,"url":"http://patchwork.ozlabs.org/api/series/4400/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4400","date":"2017-09-21T14:29:47","name":"mmc: Add support for HS200 and UHS modes","version":2,"mbox":"http://patchwork.ozlabs.org/series/4400/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816894/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816894/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506004223;\n\tbh=I73dajOX/VllT74loarTpXKPaN7wtBJ+IYCp8zKhGBM=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=NfusvhWdHkql3+Gc8l6X4zPKzVs4YiLaaNahRR4bSHjBZ7ixJmAOObpiHosKm4Yaj\n\tnnoN8LvAtnSBLmuq2Q/sESewD7xM+ohaLMDKYABfW43dtZ5jbdN4LU3k2HCjf67YMD\n\t+SIBYaNGWxA/uhl8r3sweNZOg7hQ0NqlUVdM1OHY=","From":"Jean-Jacques Hiblot ","To":", , ,\n\t","Date":"Thu, 21 Sep 2017 16:29:49 +0200","Message-ID":"<1506004213-22620-3-git-send-email-jjhiblot@ti.com>","X-Mailer":"git-send-email 1.9.1","In-Reply-To":"<1506004213-22620-1-git-send-email-jjhiblot@ti.com>","References":"<1506004213-22620-1-git-send-email-jjhiblot@ti.com>","MIME-Version":"1.0","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Cc":"u-boot@lists.denx.de","Subject":"[U-Boot] [PATCH v2 02/26] mmc: split mmc_startup()","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"No functionnal change here. The function is really big and can be split.\nThe part related to bus configuration are put in 2 separate functions: one\nfor MMC and one for SD.\n\nSigned-off-by: Jean-Jacques Hiblot \nReviewed-by: Simon Glass \n---\n drivers/mmc/mmc.c | 274 +++++++++++++++++++++++++++++-------------------------\n 1 file changed, 148 insertions(+), 126 deletions(-)","diff":"diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c\nindex 11285be..1946875 100644\n--- a/drivers/mmc/mmc.c\n+++ b/drivers/mmc/mmc.c\n@@ -1103,6 +1103,152 @@ static void mmc_set_bus_width(struct mmc *mmc, uint width)\n \tmmc_set_ios(mmc);\n }\n \n+static int sd_select_bus_freq_width(struct mmc *mmc)\n+{\n+\tint err;\n+\tstruct mmc_cmd cmd;\n+\n+\terr = sd_change_freq(mmc);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* Restrict card's capabilities by what the host can do */\n+\tmmc->card_caps &= mmc->cfg->host_caps;\n+\n+\tif (mmc->card_caps & MMC_MODE_4BIT) {\n+\t\tcmd.cmdidx = MMC_CMD_APP_CMD;\n+\t\tcmd.resp_type = MMC_RSP_R1;\n+\t\tcmd.cmdarg = mmc->rca << 16;\n+\n+\t\terr = mmc_send_cmd(mmc, &cmd, NULL);\n+\t\tif (err)\n+\t\t\treturn err;\n+\n+\t\tcmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;\n+\t\tcmd.resp_type = MMC_RSP_R1;\n+\t\tcmd.cmdarg = 2;\n+\t\terr = mmc_send_cmd(mmc, &cmd, NULL);\n+\t\tif (err)\n+\t\t\treturn err;\n+\n+\t\tmmc_set_bus_width(mmc, 4);\n+\t}\n+\n+\terr = sd_read_ssr(mmc);\n+\tif (err)\n+\t\treturn err;\n+\n+\tif (mmc->card_caps & MMC_MODE_HS)\n+\t\tmmc->tran_speed = 50000000;\n+\telse\n+\t\tmmc->tran_speed = 25000000;\n+\n+\treturn 0;\n+}\n+\n+static int mmc_select_bus_freq_width(struct mmc *mmc, const u8 *ext_csd)\n+{\n+\tALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);\n+\t/* An array of possible bus widths in order of preference */\n+\tstatic const unsigned int ext_csd_bits[] = {\n+\t\tEXT_CSD_DDR_BUS_WIDTH_8,\n+\t\tEXT_CSD_DDR_BUS_WIDTH_4,\n+\t\tEXT_CSD_BUS_WIDTH_8,\n+\t\tEXT_CSD_BUS_WIDTH_4,\n+\t\tEXT_CSD_BUS_WIDTH_1,\n+\t};\n+\t/* An array to map CSD bus widths to host cap bits */\n+\tstatic const unsigned int ext_to_hostcaps[] = {\n+\t\t[EXT_CSD_DDR_BUS_WIDTH_4] =\n+\t\t\tMMC_MODE_DDR_52MHz | MMC_MODE_4BIT,\n+\t\t[EXT_CSD_DDR_BUS_WIDTH_8] =\n+\t\t\tMMC_MODE_DDR_52MHz | MMC_MODE_8BIT,\n+\t\t[EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,\n+\t\t[EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,\n+\t};\n+\t/* An array to map chosen bus width to an integer */\n+\tstatic const unsigned int widths[] = {\n+\t\t8, 4, 8, 4, 1,\n+\t};\n+\tint err;\n+\tint idx;\n+\n+\terr = mmc_change_freq(mmc);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* Restrict card's capabilities by what the host can do */\n+\tmmc->card_caps &= mmc->cfg->host_caps;\n+\n+\t/* Only version 4 of MMC supports wider bus widths */\n+\tif (mmc->version < MMC_VERSION_4)\n+\t\treturn 0;\n+\n+\tfor (idx = 0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {\n+\t\tunsigned int extw = ext_csd_bits[idx];\n+\t\tunsigned int caps = ext_to_hostcaps[extw];\n+\t\t/*\n+\t\t * If the bus width is still not changed,\n+\t\t * don't try to set the default again.\n+\t\t * Otherwise, recover from switch attempts\n+\t\t * by switching to 1-bit bus width.\n+\t\t */\n+\t\tif (extw == EXT_CSD_BUS_WIDTH_1 &&\n+\t\t mmc->bus_width == 1) {\n+\t\t\terr = 0;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/*\n+\t\t * Check to make sure the card and controller support\n+\t\t * these capabilities\n+\t\t */\n+\t\tif ((mmc->card_caps & caps) != caps)\n+\t\t\tcontinue;\n+\n+\t\terr = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,\n+\t\t\t\t EXT_CSD_BUS_WIDTH, extw);\n+\n+\t\tif (err)\n+\t\t\tcontinue;\n+\n+\t\tmmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;\n+\t\tmmc_set_bus_width(mmc, widths[idx]);\n+\n+\t\terr = mmc_send_ext_csd(mmc, test_csd);\n+\n+\t\tif (err)\n+\t\t\tcontinue;\n+\n+\t\t/* Only compare read only fields */\n+\t\tif (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]\n+\t\t\t== test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&\n+\t\t ext_csd[EXT_CSD_HC_WP_GRP_SIZE]\n+\t\t\t== test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&\n+\t\t ext_csd[EXT_CSD_REV]\n+\t\t\t== test_csd[EXT_CSD_REV] &&\n+\t\t ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]\n+\t\t\t== test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&\n+\t\t memcmp(&ext_csd[EXT_CSD_SEC_CNT],\n+\t\t\t &test_csd[EXT_CSD_SEC_CNT], 4) == 0)\n+\t\t\tbreak;\n+\n+\t\terr = -EBADMSG;\n+\t}\n+\n+\tif (err)\n+\t\treturn err;\n+\n+\tif (mmc->card_caps & MMC_MODE_HS) {\n+\t\tif (mmc->card_caps & MMC_MODE_HS_52MHz)\n+\t\t\tmmc->tran_speed = 52000000;\n+\t\telse\n+\t\t\tmmc->tran_speed = 26000000;\n+\t}\n+\n+\treturn err;\n+}\n+\n static int mmc_startup(struct mmc *mmc)\n {\n \tint err, i;\n@@ -1110,7 +1256,6 @@ static int mmc_startup(struct mmc *mmc)\n \tu64 cmult, csize, capacity;\n \tstruct mmc_cmd cmd;\n \tALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);\n-\tALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);\n \tbool has_parts = false;\n \tbool part_completed;\n \tstruct blk_desc *bdesc;\n@@ -1415,136 +1560,13 @@ static int mmc_startup(struct mmc *mmc)\n \t\treturn err;\n \n \tif (IS_SD(mmc))\n-\t\terr = sd_change_freq(mmc);\n+\t\terr = sd_select_bus_freq_width(mmc);\n \telse\n-\t\terr = mmc_change_freq(mmc);\n+\t\terr = mmc_select_bus_freq_width(mmc, ext_csd);\n \n \tif (err)\n \t\treturn err;\n \n-\t/* Restrict card's capabilities by what the host can do */\n-\tmmc->card_caps &= mmc->cfg->host_caps;\n-\n-\tif (IS_SD(mmc)) {\n-\t\tif (mmc->card_caps & MMC_MODE_4BIT) {\n-\t\t\tcmd.cmdidx = MMC_CMD_APP_CMD;\n-\t\t\tcmd.resp_type = MMC_RSP_R1;\n-\t\t\tcmd.cmdarg = mmc->rca << 16;\n-\n-\t\t\terr = mmc_send_cmd(mmc, &cmd, NULL);\n-\t\t\tif (err)\n-\t\t\t\treturn err;\n-\n-\t\t\tcmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;\n-\t\t\tcmd.resp_type = MMC_RSP_R1;\n-\t\t\tcmd.cmdarg = 2;\n-\t\t\terr = mmc_send_cmd(mmc, &cmd, NULL);\n-\t\t\tif (err)\n-\t\t\t\treturn err;\n-\n-\t\t\tmmc_set_bus_width(mmc, 4);\n-\t\t}\n-\n-\t\terr = sd_read_ssr(mmc);\n-\t\tif (err)\n-\t\t\treturn err;\n-\n-\t\tif (mmc->card_caps & MMC_MODE_HS)\n-\t\t\tmmc->tran_speed = 50000000;\n-\t\telse\n-\t\t\tmmc->tran_speed = 25000000;\n-\t} else if (mmc->version >= MMC_VERSION_4) {\n-\t\t/* Only version 4 of MMC supports wider bus widths */\n-\t\tint idx;\n-\n-\t\t/* An array of possible bus widths in order of preference */\n-\t\tstatic unsigned ext_csd_bits[] = {\n-\t\t\tEXT_CSD_DDR_BUS_WIDTH_8,\n-\t\t\tEXT_CSD_DDR_BUS_WIDTH_4,\n-\t\t\tEXT_CSD_BUS_WIDTH_8,\n-\t\t\tEXT_CSD_BUS_WIDTH_4,\n-\t\t\tEXT_CSD_BUS_WIDTH_1,\n-\t\t};\n-\n-\t\t/* An array to map CSD bus widths to host cap bits */\n-\t\tstatic unsigned ext_to_hostcaps[] = {\n-\t\t\t[EXT_CSD_DDR_BUS_WIDTH_4] =\n-\t\t\t\tMMC_MODE_DDR_52MHz | MMC_MODE_4BIT,\n-\t\t\t[EXT_CSD_DDR_BUS_WIDTH_8] =\n-\t\t\t\tMMC_MODE_DDR_52MHz | MMC_MODE_8BIT,\n-\t\t\t[EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,\n-\t\t\t[EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,\n-\t\t};\n-\n-\t\t/* An array to map chosen bus width to an integer */\n-\t\tstatic unsigned widths[] = {\n-\t\t\t8, 4, 8, 4, 1,\n-\t\t};\n-\n-\t\tfor (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {\n-\t\t\tunsigned int extw = ext_csd_bits[idx];\n-\t\t\tunsigned int caps = ext_to_hostcaps[extw];\n-\n-\t\t\t/*\n-\t\t\t * If the bus width is still not changed,\n-\t\t\t * don't try to set the default again.\n-\t\t\t * Otherwise, recover from switch attempts\n-\t\t\t * by switching to 1-bit bus width.\n-\t\t\t */\n-\t\t\tif (extw == EXT_CSD_BUS_WIDTH_1 &&\n-\t\t\t\t\tmmc->bus_width == 1) {\n-\t\t\t\terr = 0;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\n-\t\t\t/*\n-\t\t\t * Check to make sure the card and controller support\n-\t\t\t * these capabilities\n-\t\t\t */\n-\t\t\tif ((mmc->card_caps & caps) != caps)\n-\t\t\t\tcontinue;\n-\n-\t\t\terr = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,\n-\t\t\t\t\tEXT_CSD_BUS_WIDTH, extw);\n-\n-\t\t\tif (err)\n-\t\t\t\tcontinue;\n-\n-\t\t\tmmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;\n-\t\t\tmmc_set_bus_width(mmc, widths[idx]);\n-\n-\t\t\terr = mmc_send_ext_csd(mmc, test_csd);\n-\n-\t\t\tif (err)\n-\t\t\t\tcontinue;\n-\n-\t\t\t/* Only compare read only fields */\n-\t\t\tif (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]\n-\t\t\t\t== test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&\n-\t\t\t ext_csd[EXT_CSD_HC_WP_GRP_SIZE]\n-\t\t\t\t== test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&\n-\t\t\t ext_csd[EXT_CSD_REV]\n-\t\t\t\t== test_csd[EXT_CSD_REV] &&\n-\t\t\t ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]\n-\t\t\t\t== test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&\n-\t\t\t memcmp(&ext_csd[EXT_CSD_SEC_CNT],\n-\t\t\t\t &test_csd[EXT_CSD_SEC_CNT], 4) == 0)\n-\t\t\t\tbreak;\n-\t\t\telse\n-\t\t\t\terr = -EBADMSG;\n-\t\t}\n-\n-\t\tif (err)\n-\t\t\treturn err;\n-\n-\t\tif (mmc->card_caps & MMC_MODE_HS) {\n-\t\t\tif (mmc->card_caps & MMC_MODE_HS_52MHz)\n-\t\t\t\tmmc->tran_speed = 52000000;\n-\t\t\telse\n-\t\t\t\tmmc->tran_speed = 26000000;\n-\t\t}\n-\t}\n-\n \tmmc_set_clock(mmc, mmc->tran_speed);\n \n \t/* Fix the block length for DDR mode */\n","prefixes":["U-Boot","v2","02/26"]}