{"id":816815,"url":"http://patchwork.ozlabs.org/api/patches/816815/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/patch/1505992913-107256-6-git-send-email-linyunsheng@huawei.com/","project":{"id":7,"url":"http://patchwork.ozlabs.org/api/projects/7/?format=json","name":"Linux network development","link_name":"netdev","list_id":"netdev.vger.kernel.org","list_email":"netdev@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505992913-107256-6-git-send-email-linyunsheng@huawei.com>","list_archive_url":null,"date":"2017-09-21T11:21:48","name":"[net-next,05/10] net: hns3: Add tc-based TM support for sriov enabled port","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":true,"hash":"b8378833737a9d70ec8ddb6d81ae4aeeeaa0551e","submitter":{"id":71804,"url":"http://patchwork.ozlabs.org/api/people/71804/?format=json","name":"Yunsheng Lin","email":"linyunsheng@huawei.com"},"delegate":{"id":34,"url":"http://patchwork.ozlabs.org/api/users/34/?format=json","username":"davem","first_name":"David","last_name":"Miller","email":"davem@davemloft.net"},"mbox":"http://patchwork.ozlabs.org/project/netdev/patch/1505992913-107256-6-git-send-email-linyunsheng@huawei.com/mbox/","series":[{"id":4360,"url":"http://patchwork.ozlabs.org/api/series/4360/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/list/?series=4360","date":"2017-09-21T11:21:52","name":"Add support for DCB feature in hns3 driver","version":1,"mbox":"http://patchwork.ozlabs.org/series/4360/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816815/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816815/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyZ451ZyQz9t3m\n\tfor ;\n\tThu, 21 Sep 2017 21:23:33 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751848AbdIULWZ (ORCPT );\n\tThu, 21 Sep 2017 07:22:25 -0400","from szxga04-in.huawei.com ([45.249.212.190]:6956 \"EHLO\n\tszxga04-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751679AbdIULWW (ORCPT\n\t); Thu, 21 Sep 2017 07:22:22 -0400","from 172.30.72.60 (EHLO DGGEMS408-HUB.china.huawei.com)\n\t([172.30.72.60])\n\tby dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DHR44638; Thu, 21 Sep 2017 19:22:19 +0800 (CST)","from localhost.localdomain (10.67.212.75) by\n\tDGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP\n\tServer id 14.3.301.0; Thu, 21 Sep 2017 19:22:09 +0800"],"From":"Yunsheng Lin ","To":"","CC":", ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ","Subject":"[PATCH net-next 05/10] net: hns3: Add tc-based TM support for sriov\n\tenabled port","Date":"Thu, 21 Sep 2017 19:21:48 +0800","Message-ID":"<1505992913-107256-6-git-send-email-linyunsheng@huawei.com>","X-Mailer":"git-send-email 1.9.1","In-Reply-To":"<1505992913-107256-1-git-send-email-linyunsheng@huawei.com>","References":"<1505992913-107256-1-git-send-email-linyunsheng@huawei.com>","MIME-Version":"1.0","Content-Type":"text/plain","X-Originating-IP":"[10.67.212.75]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A090204.59C3A0EB.039F, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"09e54ef2e8ba5f4d03a90245e93bb5c2","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"},"content":"When sriov is enabled and TM is in tc-based mode, vf's TM\nparameters is not set in TM initialization process.\nThis patch add the tc_based TM support for sriov enabled\nusing the information in vport struct.\n\nSigned-off-by: Yunsheng Lin \n---\n .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 49 ++++++++++++++--------\n 1 file changed, 31 insertions(+), 18 deletions(-)","diff":"diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c\nindex 33090d0..2bc7d63c 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c\n@@ -389,13 +389,13 @@ static int hclge_tm_pri_schd_mode_cfg(struct hclge_dev *hdev, u8 pri_id)\n \treturn hclge_cmd_send(&hdev->hw, &desc, 1);\n }\n \n-static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id)\n+static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id, u8 mode)\n {\n \tstruct hclge_desc desc;\n \n \thclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, false);\n \n-\tif (hdev->tm_info.tc_info[qs_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR)\n+\tif (mode == HCLGE_SCH_MODE_DWRR)\n \t\tdesc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);\n \telse\n \t\tdesc.data[1] = 0;\n@@ -639,17 +639,18 @@ static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev)\n {\n \tstruct hclge_vport *vport = hdev->vport;\n \tint ret;\n-\tu32 i;\n+\tu32 i, k;\n \n \tif (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {\n \t\t/* Cfg qs -> pri mapping, one by one mapping */\n-\t\tfor (i = 0; i < hdev->tm_info.num_tc; i++) {\n-\t\t\tret = hclge_tm_qs_to_pri_map_cfg(hdev, i, i);\n-\t\t\tif (ret)\n-\t\t\t\treturn ret;\n-\t\t}\n+\t\tfor (k = 0; k < hdev->num_alloc_vport; k++)\n+\t\t\tfor (i = 0; i < hdev->tm_info.num_tc; i++) {\n+\t\t\t\tret = hclge_tm_qs_to_pri_map_cfg(\n+\t\t\t\t\thdev, vport[k].qs_offset + i, i);\n+\t\t\t\tif (ret)\n+\t\t\t\t\treturn ret;\n+\t\t\t}\n \t} else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) {\n-\t\tint k;\n \t\t/* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */\n \t\tfor (k = 0; k < hdev->num_alloc_vport; k++)\n \t\t\tfor (i = 0; i < HNAE3_MAX_TC; i++) {\n@@ -798,10 +799,11 @@ static int hclge_tm_pri_shaper_cfg(struct hclge_dev *hdev)\n \n static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)\n {\n+\tstruct hclge_vport *vport = hdev->vport;\n \tstruct hclge_pg_info *pg_info;\n \tu8 dwrr;\n \tint ret;\n-\tu32 i;\n+\tu32 i, k;\n \n \tfor (i = 0; i < hdev->tm_info.num_tc; i++) {\n \t\tpg_info =\n@@ -812,9 +814,13 @@ static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)\n \t\tif (ret)\n \t\t\treturn ret;\n \n-\t\tret = hclge_tm_qs_weight_cfg(hdev, i, dwrr);\n-\t\tif (ret)\n-\t\t\treturn ret;\n+\t\tfor (k = 0; k < hdev->num_alloc_vport; k++) {\n+\t\t\tret = hclge_tm_qs_weight_cfg(\n+\t\t\t\thdev, vport[k].qs_offset + i,\n+\t\t\t\tvport[k].dwrr);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t}\n \t}\n \n \treturn 0;\n@@ -945,7 +951,10 @@ static int hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport *vport)\n \t\treturn ret;\n \n \tfor (i = 0; i < kinfo->num_tc; i++) {\n-\t\tret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i);\n+\t\tu8 sch_mode = hdev->tm_info.tc_info[i].tc_sch_mode;\n+\n+\t\tret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i,\n+\t\t\t\t\t\tsch_mode);\n \t\tif (ret)\n \t\t\treturn ret;\n \t}\n@@ -957,7 +966,7 @@ static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev)\n {\n \tstruct hclge_vport *vport = hdev->vport;\n \tint ret;\n-\tu8 i;\n+\tu8 i, k;\n \n \tif (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {\n \t\tfor (i = 0; i < hdev->tm_info.num_tc; i++) {\n@@ -965,9 +974,13 @@ static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev)\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n \n-\t\t\tret = hclge_tm_qs_schd_mode_cfg(hdev, i);\n-\t\t\tif (ret)\n-\t\t\t\treturn ret;\n+\t\t\tfor (k = 0; k < hdev->num_alloc_vport; k++) {\n+\t\t\t\tret = hclge_tm_qs_schd_mode_cfg(\n+\t\t\t\t\thdev, vport[k].qs_offset + i,\n+\t\t\t\t\tHCLGE_SCH_MODE_DWRR);\n+\t\t\t\tif (ret)\n+\t\t\t\t\treturn ret;\n+\t\t\t}\n \t\t}\n \t} else {\n \t\tfor (i = 0; i < hdev->num_alloc_vport; i++) {\n","prefixes":["net-next","05/10"]}