{"id":816748,"url":"http://patchwork.ozlabs.org/api/patches/816748/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/7a78ecd89b459d7779e2238583f2837ba4d17a0d.1505980364.git.sean.wang@mediatek.com/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<7a78ecd89b459d7779e2238583f2837ba4d17a0d.1505980364.git.sean.wang@mediatek.com>","list_archive_url":null,"date":"2017-09-21T08:26:51","name":"[v4,1/7] dt-bindings: arm: mediatek: add MT7622 string to the PMIC wrapper doc","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"c8cdb394ac3b3f61231904d378954f604d3d7812","submitter":{"id":69660,"url":"http://patchwork.ozlabs.org/api/people/69660/?format=json","name":"Sean Wang","email":"sean.wang@mediatek.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/7a78ecd89b459d7779e2238583f2837ba4d17a0d.1505980364.git.sean.wang@mediatek.com/mbox/","series":[{"id":4328,"url":"http://patchwork.ozlabs.org/api/series/4328/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=4328","date":"2017-09-21T08:26:50","name":"Add PMIC support to MediaTek MT7622 SoC","version":4,"mbox":"http://patchwork.ozlabs.org/series/4328/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816748/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816748/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyVBh5D4Rz9sBZ\n\tfor ;\n\tThu, 21 Sep 2017 18:29:00 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752012AbdIUI1G (ORCPT\n\t);\n\tThu, 21 Sep 2017 04:27:06 -0400","from mailgw02.mediatek.com ([210.61.82.184]:64723 \"EHLO\n\tmailgw02.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by\n\tvger.kernel.org with ESMTP id S1751606AbdIUI1F (ORCPT\n\t); Thu, 21 Sep 2017 04:27:05 -0400","from mtkcas09.mediatek.inc [(172.21.101.178)] by\n\tmailgw02.mediatek.com (envelope-from )\n\t(mhqrelay.mediatek.com ESMTP with TLS)\n\twith ESMTP id 421604794; Thu, 21 Sep 2017 16:27:02 +0800","from mtkcas08.mediatek.inc (172.21.101.126) by\n\tmtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server\n\t(TLS) id 15.0.1210.3; Thu, 21 Sep 2017 16:26:31 +0800","from mtkswgap22.mediatek.inc (172.21.77.33) by\n\tmtkcas08.mediatek.inc\n\t(172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via\n\tFrontend Transport; Thu, 21 Sep 2017 16:26:25 +0800"],"X-UUID":"51b33d832f864f8e85d932d4375fc31a-20170921","From":"","To":", ,\n\t, ,\n\t","CC":", ,\n\t,\n\t, Sean Wang ","Subject":"[PATCH v4 1/7] dt-bindings: arm: mediatek: add MT7622 string to the\n\tPMIC wrapper doc","Date":"Thu, 21 Sep 2017 16:26:51 +0800","Message-ID":"<7a78ecd89b459d7779e2238583f2837ba4d17a0d.1505980364.git.sean.wang@mediatek.com>","X-Mailer":"git-send-email 1.7.9.5","In-Reply-To":"","References":"","MIME-Version":"1.0","Content-Type":"text/plain","X-MTK":"N","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"From: Sean Wang \n\nSigned-off-by: Chenglin Xu \nSigned-off-by: Sean Wang \nAcked-by: Rob Herring \n---\n Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 1 +\n 1 file changed, 1 insertion(+)","diff":"diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt\nindex 107700d..bd97f22 100644\n--- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt\n+++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt\n@@ -19,6 +19,7 @@ IP Pairing\n Required properties in pwrap device node.\n - compatible:\n \t\"mediatek,mt2701-pwrap\" for MT2701/7623 SoCs\n+\t\"mediatek,mt7622-pwrap\" for MT7622 SoCs\n \t\"mediatek,mt8135-pwrap\" for MT8135 SoCs\n \t\"mediatek,mt8173-pwrap\" for MT8173 SoCs\n - interrupts: IRQ for pwrap in SOC\n","prefixes":["v4","1/7"]}