{"id":816685,"url":"http://patchwork.ozlabs.org/api/patches/816685/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20170921062911.26724-5-anarsoul@gmail.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170921062911.26724-5-anarsoul@gmail.com>","list_archive_url":null,"date":"2017-09-21T06:29:10","name":"[U-Boot,v2,4/5] sunxi: video: split out PLL configuration code","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"fd49ca7a8718875701ca19fd9dbb72add9252eca","submitter":{"id":6930,"url":"http://patchwork.ozlabs.org/api/people/6930/?format=json","name":"Vasily Khoruzhick","email":"anarsoul@gmail.com"},"delegate":{"id":1700,"url":"http://patchwork.ozlabs.org/api/users/1700/?format=json","username":"ag","first_name":"Anatolij","last_name":"Gustschin","email":"agust@denx.de"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20170921062911.26724-5-anarsoul@gmail.com/mbox/","series":[{"id":4307,"url":"http://patchwork.ozlabs.org/api/series/4307/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4307","date":"2017-09-21T06:29:06","name":"sunxi: video: add DE2 LCD and ANX6345 drivers","version":2,"mbox":"http://patchwork.ozlabs.org/series/4307/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816685/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816685/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"It will be reused in new DM LCD driver.\n\nSigned-off-by: Vasily Khoruzhick \n---\nv2: - no changes\n\n arch/arm/include/asm/arch-sunxi/lcdc.h | 2 +\n drivers/video/sunxi/lcdc.c | 117 ++++++++++++++++++++++++++++++-\n drivers/video/sunxi/sunxi_display.c | 121 ++-------------------------------\n 3 files changed, 124 insertions(+), 116 deletions(-)","diff":"diff --git a/arch/arm/include/asm/arch-sunxi/lcdc.h b/arch/arm/include/asm/arch-sunxi/lcdc.h\nindex a751698b4f..5d9253aaa5 100644\n--- a/arch/arm/include/asm/arch-sunxi/lcdc.h\n+++ b/arch/arm/include/asm/arch-sunxi/lcdc.h\n@@ -124,5 +124,7 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,\n void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,\n \t\t\t const struct display_timing *mode,\n \t\t\t bool ext_hvsync, bool is_composite);\n+void lcdc_pll_set(struct sunxi_ccm_reg * const ccm, int tcon,\n+\t\t int dotclock, int *clk_div, int *clk_double);\n \n #endif /* _LCDC_H */\ndiff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c\nindex 7d215b713e..023a30cb1e 100644\n--- a/drivers/video/sunxi/lcdc.c\n+++ b/drivers/video/sunxi/lcdc.c\n@@ -10,6 +10,7 @@\n \n #include \n \n+#include \n #include \n #include \n \n@@ -100,7 +101,7 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,\n \twritel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |\n \t SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);\n \n-#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL\n+#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_VIDEO_DE2)\n \twritel(SUNXI_LCDC_X(mode->hsync_len.typ) |\n \t SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon0_timing_sync);\n \n@@ -207,3 +208,117 @@ void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,\n \t\t\t\tSUNXI_LCDC_MUX_CTRL_SRC0(1));\n #endif\n }\n+\n+void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,\n+\t\t int *clk_div, int *clk_double)\n+{\n+\tint value, n, m, min_m, max_m, diff;\n+\tint best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;\n+\tint best_double = 0;\n+\tbool use_mipi_pll = false;\n+\n+\tif (tcon == 0) {\n+#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_SUNXI_DE2)\n+\t\tmin_m = 6;\n+\t\tmax_m = 127;\n+#endif\n+#ifdef CONFIG_VIDEO_LCD_IF_LVDS\n+\t\tmin_m = max_m = 7;\n+#endif\n+\t} else {\n+\t\tmin_m = 1;\n+\t\tmax_m = 15;\n+\t}\n+\n+\t/*\n+\t * Find the lowest divider resulting in a matching clock, if there\n+\t * is no match, pick the closest lower clock, as monitors tend to\n+\t * not sync to higher frequencies.\n+\t */\n+\tfor (m = min_m; m <= max_m; m++) {\n+#ifndef CONFIG_SUNXI_DE2\n+\t\tn = (m * dotclock) / 3000;\n+\n+\t\tif ((n >= 9) && (n <= 127)) {\n+\t\t\tvalue = (3000 * n) / m;\n+\t\t\tdiff = dotclock - value;\n+\t\t\tif (diff < best_diff) {\n+\t\t\t\tbest_diff = diff;\n+\t\t\t\tbest_m = m;\n+\t\t\t\tbest_n = n;\n+\t\t\t\tbest_double = 0;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* These are just duplicates */\n+\t\tif (!(m & 1))\n+\t\t\tcontinue;\n+#endif\n+\n+\t\t/* No double clock on DE2 */\n+\t\tn = (m * dotclock) / 6000;\n+\t\tif ((n >= 9) && (n <= 127)) {\n+\t\t\tvalue = (6000 * n) / m;\n+\t\t\tdiff = dotclock - value;\n+\t\t\tif (diff < best_diff) {\n+\t\t\t\tbest_diff = diff;\n+\t\t\t\tbest_m = m;\n+\t\t\t\tbest_n = n;\n+\t\t\t\tbest_double = 1;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+#ifdef CONFIG_MACH_SUN6I\n+\t/*\n+\t * Use the MIPI pll if we've been unable to find any matching setting\n+\t * for PLL3, this happens with high dotclocks because of min_m = 6.\n+\t */\n+\tif (tcon == 0 && best_n == 0) {\n+\t\tuse_mipi_pll = true;\n+\t\tbest_m = 6; /* Minimum m for tcon0 */\n+\t}\n+\n+\tif (use_mipi_pll) {\n+\t\tclock_set_pll3(297000000); /* Fix the video pll at 297 MHz */\n+\t\tclock_set_mipi_pll(best_m * dotclock * 1000);\n+\t\tdebug(\"dotclock: %dkHz = %dkHz via mipi pll\\n\",\n+\t\t dotclock, clock_get_mipi_pll() / best_m / 1000);\n+\t} else\n+#endif\n+\t{\n+\t\tclock_set_pll3(best_n * 3000000);\n+\t\tdebug(\"dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\\n\",\n+\t\t dotclock,\n+\t\t (best_double + 1) * clock_get_pll3() / best_m / 1000,\n+\t\t best_double + 1, best_n, best_m);\n+\t}\n+\n+\tif (tcon == 0) {\n+\t\tu32 pll;\n+\n+\t\tif (use_mipi_pll)\n+\t\t\tpll = CCM_LCD_CH0_CTRL_MIPI_PLL;\n+\t\telse if (best_double)\n+\t\t\tpll = CCM_LCD_CH0_CTRL_PLL3_2X;\n+\t\telse\n+\t\t\tpll = CCM_LCD_CH0_CTRL_PLL3;\n+\n+\t\twritel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST | pll,\n+\t\t &ccm->lcd0_clk_cfg);\n+\t}\n+#ifndef CONFIG_SUNXI_DE2\n+\telse {\n+\t\twritel(CCM_LCD_CH1_CTRL_GATE |\n+\t\t (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :\n+\t\t\t\t CCM_LCD_CH1_CTRL_PLL3) |\n+\t\t CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);\n+\t\tif (sunxi_is_composite())\n+\t\t\tsetbits_le32(&ccm->lcd0_ch1_clk_cfg,\n+\t\t\t\t CCM_LCD_CH1_CTRL_HALF_SCLK1);\n+\t}\n+#endif\n+\n+\t*clk_div = best_m;\n+\t*clk_double = best_double;\n+}\ndiff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c\nindex de768ba94a..f3db125305 100644\n--- a/drivers/video/sunxi/sunxi_display.c\n+++ b/drivers/video/sunxi/sunxi_display.c\n@@ -515,119 +515,6 @@ static void sunxi_composer_enable(void)\n \tsetbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);\n }\n \n-/*\n- * LCDC, what allwinner calls a CRTC, so timing controller and serializer.\n- */\n-static void sunxi_lcdc_pll_set(int tcon, int dotclock,\n-\t\t\t int *clk_div, int *clk_double)\n-{\n-\tstruct sunxi_ccm_reg * const ccm =\n-\t\t(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;\n-\tint value, n, m, min_m, max_m, diff;\n-\tint best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;\n-\tint best_double = 0;\n-\tbool use_mipi_pll = false;\n-\n-\tif (tcon == 0) {\n-#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL\n-\t\tmin_m = 6;\n-\t\tmax_m = 127;\n-#endif\n-#ifdef CONFIG_VIDEO_LCD_IF_LVDS\n-\t\tmin_m = max_m = 7;\n-#endif\n-\t} else {\n-\t\tmin_m = 1;\n-\t\tmax_m = 15;\n-\t}\n-\n-\t/*\n-\t * Find the lowest divider resulting in a matching clock, if there\n-\t * is no match, pick the closest lower clock, as monitors tend to\n-\t * not sync to higher frequencies.\n-\t */\n-\tfor (m = min_m; m <= max_m; m++) {\n-\t\tn = (m * dotclock) / 3000;\n-\n-\t\tif ((n >= 9) && (n <= 127)) {\n-\t\t\tvalue = (3000 * n) / m;\n-\t\t\tdiff = dotclock - value;\n-\t\t\tif (diff < best_diff) {\n-\t\t\t\tbest_diff = diff;\n-\t\t\t\tbest_m = m;\n-\t\t\t\tbest_n = n;\n-\t\t\t\tbest_double = 0;\n-\t\t\t}\n-\t\t}\n-\n-\t\t/* These are just duplicates */\n-\t\tif (!(m & 1))\n-\t\t\tcontinue;\n-\n-\t\tn = (m * dotclock) / 6000;\n-\t\tif ((n >= 9) && (n <= 127)) {\n-\t\t\tvalue = (6000 * n) / m;\n-\t\t\tdiff = dotclock - value;\n-\t\t\tif (diff < best_diff) {\n-\t\t\t\tbest_diff = diff;\n-\t\t\t\tbest_m = m;\n-\t\t\t\tbest_n = n;\n-\t\t\t\tbest_double = 1;\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-#ifdef CONFIG_MACH_SUN6I\n-\t/*\n-\t * Use the MIPI pll if we've been unable to find any matching setting\n-\t * for PLL3, this happens with high dotclocks because of min_m = 6.\n-\t */\n-\tif (tcon == 0 && best_n == 0) {\n-\t\tuse_mipi_pll = true;\n-\t\tbest_m = 6; /* Minimum m for tcon0 */\n-\t}\n-\n-\tif (use_mipi_pll) {\n-\t\tclock_set_pll3(297000000); /* Fix the video pll at 297 MHz */\n-\t\tclock_set_mipi_pll(best_m * dotclock * 1000);\n-\t\tdebug(\"dotclock: %dkHz = %dkHz via mipi pll\\n\",\n-\t\t dotclock, clock_get_mipi_pll() / best_m / 1000);\n-\t} else\n-#endif\n-\t{\n-\t\tclock_set_pll3(best_n * 3000000);\n-\t\tdebug(\"dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\\n\",\n-\t\t dotclock,\n-\t\t (best_double + 1) * clock_get_pll3() / best_m / 1000,\n-\t\t best_double + 1, best_n, best_m);\n-\t}\n-\n-\tif (tcon == 0) {\n-\t\tu32 pll;\n-\n-\t\tif (use_mipi_pll)\n-\t\t\tpll = CCM_LCD_CH0_CTRL_MIPI_PLL;\n-\t\telse if (best_double)\n-\t\t\tpll = CCM_LCD_CH0_CTRL_PLL3_2X;\n-\t\telse\n-\t\t\tpll = CCM_LCD_CH0_CTRL_PLL3;\n-\n-\t\twritel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST | pll,\n-\t\t &ccm->lcd0_ch0_clk_cfg);\n-\t} else {\n-\t\twritel(CCM_LCD_CH1_CTRL_GATE |\n-\t\t (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :\n-\t\t\t\t CCM_LCD_CH1_CTRL_PLL3) |\n-\t\t CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);\n-\t\tif (sunxi_is_composite())\n-\t\t\tsetbits_le32(&ccm->lcd0_ch1_clk_cfg,\n-\t\t\t\t CCM_LCD_CH1_CTRL_HALF_SCLK1);\n-\t}\n-\n-\t*clk_div = best_m;\n-\t*clk_double = best_double;\n-}\n-\n static void sunxi_lcdc_init(void)\n {\n \tstruct sunxi_ccm_reg * const ccm =\n@@ -754,6 +641,8 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,\n {\n \tstruct sunxi_lcdc_reg * const lcdc =\n \t\t(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;\n+\tstruct sunxi_ccm_reg * const ccm =\n+\t\t(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;\n \tint clk_div, clk_double, pin;\n \tstruct display_timing timing;\n \n@@ -773,7 +662,7 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,\n #endif\n \t}\n \n-\tsunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);\n+\tlcdc_pll_set(ccm, 0, mode->pixclock_khz, &clk_div, &clk_double);\n \n \tsunxi_ctfb_mode_to_display_timing(mode, &timing);\n \tlcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,\n@@ -787,6 +676,8 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,\n {\n \tstruct sunxi_lcdc_reg * const lcdc =\n \t\t(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;\n+\tstruct sunxi_ccm_reg * const ccm =\n+\t\t(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;\n \tstruct display_timing timing;\n \n \tsunxi_ctfb_mode_to_display_timing(mode, &timing);\n@@ -798,7 +689,7 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,\n \t\tsunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);\n \t}\n \n-\tsunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);\n+\tlcdc_pll_set(ccm, 1, mode->pixclock_khz, clk_div, clk_double);\n }\n #endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */\n \n","prefixes":["U-Boot","v2","4/5"]}