{"id":816634,"url":"http://patchwork.ozlabs.org/api/patches/816634/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1505957212-13402-2-git-send-email-zhiyong.tao@mediatek.com/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1505957212-13402-2-git-send-email-zhiyong.tao@mediatek.com>","list_archive_url":null,"date":"2017-09-21T01:26:50","name":"[1/3] dt-bindings: adc: mt2712: add binding document","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"d2cdcd4c8eca2fe949c98803d7805f6d0996f20b","submitter":{"id":69418,"url":"http://patchwork.ozlabs.org/api/people/69418/?format=json","name":"Zhiyong Tao","email":"zhiyong.tao@mediatek.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1505957212-13402-2-git-send-email-zhiyong.tao@mediatek.com/mbox/","series":[{"id":4271,"url":"http://patchwork.ozlabs.org/api/series/4271/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=4271","date":"2017-09-21T01:26:50","name":"AUXADC: Mediatek auxadc driver for mt2712","version":1,"mbox":"http://patchwork.ozlabs.org/series/4271/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816634/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816634/checks/","tags":{},"related":[],"headers":{"Return-Path":"<devicetree-owner@vger.kernel.org>","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyJqz4s3Kz9sNr\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tThu, 21 Sep 2017 11:27:11 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751000AbdIUB1J (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tWed, 20 Sep 2017 21:27:09 -0400","from mailgw01.mediatek.com ([210.61.82.183]:23668 \"EHLO\n\tmailgw01.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by\n\tvger.kernel.org with ESMTP id S1751189AbdIUB1G (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Wed, 20 Sep 2017 21:27:06 -0400","from mtkcas06.mediatek.inc [(172.21.101.30)] by\n\tmailgw01.mediatek.com (envelope-from <zhiyong.tao@mediatek.com>)\n\t(mhqrelay.mediatek.com ESMTP with TLS)\n\twith ESMTP id 136691049; Thu, 21 Sep 2017 09:26:59 +0800","from mtkcas09.mediatek.inc (172.21.101.178) by\n\tmtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server\n\t(TLS) id 15.0.1210.3; Thu, 21 Sep 2017 09:26:47 +0800","from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc\n\t(172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via\n\tFrontend Transport; Thu, 21 Sep 2017 09:27:17 +0800"],"X-UUID":"7aa3a3f79c3b4d69bd19ec3e4144e5d0-20170921","From":"Zhiyong Tao <zhiyong.tao@mediatek.com>","To":"<robh+dt@kernel.org>, <jic23@kernel.org>, <knaack.h@gmx.de>,\n\t<lars@metafoo.de>, <pmeerw@pmeerw.net>","CC":"<srv_heupstream@mediatek.com>, <liguo.zhang@mediatek.com>,\n\t<yingjoe.chen@mediatek.com>, <sean.wang@mediatek.com>,\n\t<yt.shen@mediatek.com>, <matthias.bgg@gmail.com>,\n\t<s.hauer@pengutronix.de>, <devicetree@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,\n\t<linux-iio@vger.kernel.org>, <linux-mediatek@lists.infradead.org>,\n\tZhiyong Tao <zhiyong.tao@mediatek.com>","Subject":"[PATCH 1/3] dt-bindings: adc: mt2712: add binding document","Date":"Thu, 21 Sep 2017 09:26:50 +0800","Message-ID":"<1505957212-13402-2-git-send-email-zhiyong.tao@mediatek.com>","X-Mailer":"git-send-email 1.7.9.5","In-Reply-To":"<1505957212-13402-1-git-send-email-zhiyong.tao@mediatek.com>","References":"<1505957212-13402-1-git-send-email-zhiyong.tao@mediatek.com>","MIME-Version":"1.0","Content-Type":"text/plain","X-MTK":"N","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<devicetree.vger.kernel.org>","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"The commit adds mt2712 compatible node in binding document.\n\nSigned-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>\n---\n .../devicetree/bindings/iio/adc/mt6577_auxadc.txt  |    1 +\n 1 file changed, 1 insertion(+)","diff":"diff --git a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt\nindex 64dc484..0df9bef 100644\n--- a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt\n+++ b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt\n@@ -12,6 +12,7 @@ for the Thermal Controller which holds a phandle to the AUXADC.\n Required properties:\n   - compatible: Should be one of:\n     - \"mediatek,mt2701-auxadc\": For MT2701 family of SoCs\n+    - \"mediatek,mt2712-auxadc\": For MT2712 family of SoCs\n     - \"mediatek,mt7622-auxadc\": For MT7622 family of SoCs\n     - \"mediatek,mt8173-auxadc\": For MT8173 family of SoCs\n   - reg: Address range of the AUXADC unit.\n","prefixes":["1/3"]}