{"id":816529,"url":"http://patchwork.ozlabs.org/api/patches/816529/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/ab4b24b35e4b73354fbe79788217d5dc947d7002.1505929556.git.alistair.francis@xilinx.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2017-09-20T22:01:37","name":"[v3,2/8] xlnx-zynqmp-pmu: Add the CPU and memory","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"68814cd3acfba6b006365ad0649e5cbacaa92819","submitter":{"id":47878,"url":"http://patchwork.ozlabs.org/api/people/47878/?format=json","name":"Alistair Francis","email":"alistair.francis@xilinx.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/ab4b24b35e4b73354fbe79788217d5dc947d7002.1505929556.git.alistair.francis@xilinx.com/mbox/","series":[{"id":4241,"url":"http://patchwork.ozlabs.org/api/series/4241/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4241","date":"2017-09-20T22:01:31","name":"Add the ZynqMP PMU and IPI","version":3,"mbox":"http://patchwork.ozlabs.org/series/4241/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/816529/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/816529/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(2401047)(5005006)(8121501046)(10201501046)(3002001)(93006095)(93004095)(100000703101)(100105400095)(6055026)(6041248)(20161123564025)(20161123555025)(20161123558100)(20161123560025)(20161123562025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:CY1PR02MB1135; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CY1PR02MB1135; ","X-Forefront-PRVS":"04362AC73B","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"xilinx.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"20 Sep 2017 22:05:28.8552\n\t(UTC)","X-MS-Exchange-CrossTenant-Id":"657af505-d5df-48d0-8300-c31994686c5c","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=657af505-d5df-48d0-8300-c31994686c5c; \n\tIp=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CY1PR02MB1135","X-detected-operating-system":"by eggs.gnu.org: Windows 7 or 8 [fuzzy]","X-Received-From":"104.47.32.83","Subject":"[Qemu-devel] [PATCH v3 2/8] xlnx-zynqmp-pmu: Add the CPU and memory","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"alistair23@gmail.com, qemu-arm@nongnu.org, alistair.francis@xilinx.com","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Connect the MicroBlaze CPU and the ROM and RAM memory regions.\n\nSigned-off-by: Alistair Francis \n---\nV2:\n - Fix the pmu-cpu name\n - Use err and errp for CPU realise instead of error_fatal\n\n hw/microblaze/xlnx-zynqmp-pmu.c | 70 +++++++++++++++++++++++++++++++++++++++--\n 1 file changed, 68 insertions(+), 2 deletions(-)","diff":"diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c\nindex fc3c8b236f..b643125704 100644\n--- a/hw/microblaze/xlnx-zynqmp-pmu.c\n+++ b/hw/microblaze/xlnx-zynqmp-pmu.c\n@@ -18,8 +18,11 @@\n #include \"qemu/osdep.h\"\n #include \"qapi/error.h\"\n #include \"qemu-common.h\"\n+#include \"exec/address-spaces.h\"\n #include \"hw/boards.h\"\n+#include \"hw/qdev-properties.h\"\n #include \"cpu.h\"\n+#include \"boot.h\"\n \n /* Define the PMU device */\n \n@@ -27,21 +30,56 @@\n #define XLNX_ZYNQMP_PMU(obj) OBJECT_CHECK(XlnxZynqMPPMUState, (obj), \\\n TYPE_XLNX_ZYNQMP_PMU)\n \n+#define XLNX_ZYNQMP_PMU_ROM_SIZE 0x8000\n+#define XLNX_ZYNQMP_PMU_ROM_ADDR 0xFFD00000\n+#define XLNX_ZYNQMP_PMU_RAM_ADDR 0xFFDC0000\n+\n typedef struct XlnxZynqMPPMUState {\n /*< private >*/\n DeviceState parent_obj;\n \n /*< public >*/\n+ MicroBlazeCPU cpu;\n } XlnxZynqMPPMUState;\n \n static void xlnx_zynqmp_pmu_init(Object *obj)\n {\n+ XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(obj);\n \n+ object_initialize(&s->cpu, sizeof(s->cpu),\n+ TYPE_MICROBLAZE_CPU);\n+ object_property_add_child(obj, \"pmu-cpu\", OBJECT(&s->cpu),\n+ &error_abort);\n }\n \n static void xlnx_zynqmp_pmu_realize(DeviceState *dev, Error **errp)\n {\n-\n+ XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(dev);\n+ Error *err = NULL;\n+\n+ object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,\n+ \"base-vectors\", &error_abort);\n+ object_property_set_bool(OBJECT(&s->cpu), true, \"use-stack-protection\",\n+ &error_abort);\n+ object_property_set_uint(OBJECT(&s->cpu), 0, \"use-fpu\", &error_abort);\n+ object_property_set_uint(OBJECT(&s->cpu), 0, \"use-hw-mul\", &error_abort);\n+ object_property_set_bool(OBJECT(&s->cpu), true, \"use-barrel\",\n+ &error_abort);\n+ object_property_set_bool(OBJECT(&s->cpu), true, \"use-msr-instr\",\n+ &error_abort);\n+ object_property_set_bool(OBJECT(&s->cpu), true, \"use-pcmp-instr\",\n+ &error_abort);\n+ object_property_set_bool(OBJECT(&s->cpu), false, \"use-mmu\", &error_abort);\n+ object_property_set_bool(OBJECT(&s->cpu), true, \"endianness\",\n+ &error_abort);\n+ object_property_set_str(OBJECT(&s->cpu), \"8.40.b\", \"version\",\n+ &error_abort);\n+ object_property_set_uint(OBJECT(&s->cpu), 0, \"pvr\", &error_abort);\n+ object_property_set_bool(OBJECT(&s->cpu), true, \"realized\", &err);\n+ if (err) {\n+ error_propagate(errp, err);\n+ return;\n+ }\n }\n \n static void xlnx_zynqmp_pmu_class_init(ObjectClass *oc, void *data)\n@@ -70,7 +108,35 @@ type_init(xlnx_zynqmp_pmu_register_types)\n \n static void xlnx_zcu102_pmu_init(MachineState *machine)\n {\n-\n+ XlnxZynqMPPMUState *pmu = g_new0(XlnxZynqMPPMUState, 1);\n+ MemoryRegion *address_space_mem = get_system_memory();\n+ MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);\n+ MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);\n+\n+ /* Create the ROM */\n+ memory_region_init_rom(pmu_rom, NULL, \"xlnx-zcu102-pmu.rom\",\n+ XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);\n+ memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,\n+ pmu_rom);\n+\n+ /* Create the RAM */\n+ memory_region_init_ram(pmu_ram, NULL, \"xlnx-zcu102-pmu.ram\",\n+ machine->ram_size, &error_fatal);\n+ memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,\n+ pmu_ram);\n+\n+ /* Create the PMU device */\n+ object_initialize(pmu, sizeof(XlnxZynqMPPMUState), TYPE_XLNX_ZYNQMP_PMU);\n+ object_property_add_child(OBJECT(machine), \"pmu\", OBJECT(pmu),\n+ &error_abort);\n+ object_property_set_bool(OBJECT(pmu), true, \"realized\", &error_fatal);\n+\n+ /* Load the kernel */\n+ microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,\n+ machine->ram_size,\n+ machine->kernel_filename,\n+ machine->dtb,\n+ NULL);\n }\n \n static void xlnx_zcu102_pmu_machine_init(MachineClass *mc)\n","prefixes":["v3","2/8"]}